X-Git-Url: https://review.openocd.org/gitweb?a=blobdiff_plain;f=src%2Ftarget%2Fnds32_reg.h;h=8808cd244c436935682d4cbbf47d9df0d454370b;hb=c06ac3b5d357351e34438452a72a14e534910c6f;hp=a94194143e077594b6ac086d68db6bc45389e8d7;hpb=ceb402dc9e903d2f3f6bc8125dfed9d82b83d2d1;p=openocd.git

diff --git a/src/target/nds32_reg.h b/src/target/nds32_reg.h
index a94194143e..8808cd244c 100644
--- a/src/target/nds32_reg.h
+++ b/src/target/nds32_reg.h
@@ -1,5 +1,5 @@
 /***************************************************************************
- *   Copyright (C) 2013 by Andes Technology                                *
+ *   Copyright (C) 2013 Andes Technology                                   *
  *   Hsiangkai Wang <hkwang@andestech.com>                                 *
  *                                                                         *
  *   This program is free software; you can redistribute it and/or modify  *
@@ -13,19 +13,17 @@
  *   GNU General Public License for more details.                          *
  *                                                                         *
  *   You should have received a copy of the GNU General Public License     *
- *   along with this program; if not, write to the                         *
- *   Free Software Foundation, Inc.,                                       *
- *   51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.           *
+ *   along with this program.  If not, see <http://www.gnu.org/licenses/>. *
  ***************************************************************************/
-#ifndef __NDS32_REG_H__
-#define __NDS32_REG_H__
+
+#ifndef OPENOCD_TARGET_NDS32_REG_H
+#define OPENOCD_TARGET_NDS32_REG_H
 
 #define SRIDX(a, b, c)			((a << 7) | (b << 3) | c)
 #define NDS32_REGISTER_DISABLE		(0x0)
 
 enum nds32_reg_number_s {
-	/* general registers */
-	R0 = 0,
+	R0 = 0, /* general registers */
 	R1,
 	R2,
 	R3,
@@ -64,9 +62,7 @@ enum nds32_reg_number_s {
 	D1HI,
 	ITB,
 	IFC_LP,
-
-	/* system registers */
-	CR0,
+	CR0, /* system registers */
 	CR1,
 	CR2,
 	CR3,
@@ -99,6 +95,11 @@ enum nds32_reg_number_s {
 	IR23,
 	IR24,
 	IR25,
+	IR26,
+	IR27,
+	IR28,
+	IR29,
+	IR30,
 	MR0,
 	MR1,
 	MR2,
@@ -180,9 +181,7 @@ enum nds32_reg_number_s {
 	IDR0,
 	IDR1,
 	SECUR0,
-
-	/* audio registers */
-	D0L24,
+	D0L24, /* audio registers */
 	D1L24,
 	I0,
 	I1,
@@ -214,9 +213,7 @@ enum nds32_reg_number_s {
 	CBE1,
 	CBE2,
 	CBE3,
-
-	/* fpu */
-	FPCSR,
+	FPCSR, /* fpu */
 	FPCFG,
 	FS0,
 	FS1,
@@ -310,11 +307,19 @@ struct nds32_reg_s {
 	uint8_t size;
 };
 
+struct nds32_reg_exception_s {
+	uint32_t reg_num;
+	uint32_t ex_value_bit_pos;
+	uint32_t ex_value_mask;
+	uint32_t ex_value;
+};
+
 void nds32_reg_init(void);
 uint32_t nds32_reg_sr_index(uint32_t number);
 enum nds32_reg_type_s nds32_reg_type(uint32_t number);
 uint8_t nds32_reg_size(uint32_t number);
 const char *nds32_reg_simple_name(uint32_t number);
 const char *nds32_reg_symbolic_name(uint32_t number);
+bool nds32_reg_exception(uint32_t number, uint32_t value);
 
-#endif
+#endif /* OPENOCD_TARGET_NDS32_REG_H */