X-Git-Url: https://review.openocd.org/gitweb?a=blobdiff_plain;f=src%2Ftarget%2Fmips_m4k.c;h=4adc1f193c39818d91a715819afceb32cb659338;hb=fccb812f829e55940e26466c4cda8c25765d4f6c;hp=864ede072a4453233cef1c54df190f6060fb4262;hpb=1d4a09c2ef22dc10ec8a40183b8dd1b1102af20d;p=openocd.git diff --git a/src/target/mips_m4k.c b/src/target/mips_m4k.c index 864ede072a..4adc1f193c 100644 --- a/src/target/mips_m4k.c +++ b/src/target/mips_m4k.c @@ -4,6 +4,8 @@ * * * Copyright (C) 2008 by David T.L. Wong * * * + * Copyright (C) 2009 by David N. Claffey * + * * * This program is free software; you can redistribute it and/or modify * * it under the terms of the GNU General Public License as published by * * the Free Software Foundation; either version 2 of the License, or * @@ -30,7 +32,6 @@ #include "target_type.h" #include "register.h" - /* cli handling */ /* forward declarations */ @@ -41,7 +42,6 @@ int mips_m4k_resume(struct target *target, int current, uint32_t address, int ha int mips_m4k_step(struct target *target, int current, uint32_t address, int handle_breakpoints); int mips_m4k_read_memory(struct target *target, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer); int mips_m4k_write_memory(struct target *target, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer); -int mips_m4k_register_commands(struct command_context *cmd_ctx); int mips_m4k_init_target(struct command_context *cmd_ctx, struct target *target); int mips_m4k_target_create(struct target *target, Jim_Interp *interp); @@ -82,7 +82,6 @@ struct target_type mips_m4k_target = .add_watchpoint = mips_m4k_add_watchpoint, .remove_watchpoint = mips_m4k_remove_watchpoint, - .register_commands = mips_m4k_register_commands, .target_create = mips_m4k_target_create, .init_target = mips_m4k_init_target, .examine = mips_m4k_examine, @@ -309,7 +308,7 @@ int mips_m4k_assert_reset(struct target *target) target->state = TARGET_RESET; jtag_add_sleep(50000); - mips32_invalidate_core_regs(target); + register_cache_invalidate(mips32->core_cache); if (target->reset_halt) { @@ -410,7 +409,7 @@ int mips_m4k_resume(struct target *target, int current, uint32_t address, int ha target->debug_reason = DBG_REASON_NOTHALTED; /* registers are now invalid */ - mips32_invalidate_core_regs(target); + register_cache_invalidate(mips32->core_cache); if (!debug_execution) { @@ -467,7 +466,7 @@ int mips_m4k_step(struct target *target, int current, uint32_t address, int hand mips_ejtag_exit_debug(ejtag_info); /* registers are now invalid */ - mips32_invalidate_core_regs(target); + register_cache_invalidate(mips32->core_cache); if (breakpoint) mips_m4k_set_breakpoint(target, breakpoint); @@ -902,14 +901,6 @@ int mips_m4k_write_memory(struct target *target, uint32_t address, uint32_t size return mips32_dmaacc_write_mem(ejtag_info, address, size, count, (void *)buffer); } -int mips_m4k_register_commands(struct command_context *cmd_ctx) -{ - int retval; - - retval = mips32_register_commands(cmd_ctx); - return retval; -} - int mips_m4k_init_target(struct command_context *cmd_ctx, struct target *target) { mips32_build_reg_cache(target); @@ -972,7 +963,49 @@ int mips_m4k_examine(struct target *target) int mips_m4k_bulk_write_memory(struct target *target, uint32_t address, uint32_t count, uint8_t *buffer) { - return mips_m4k_write_memory(target, address, 4, count, buffer); + struct mips32_common *mips32 = target->arch_info; + struct mips_ejtag *ejtag_info = &mips32->ejtag_info; + struct working_area *source; + int retval; + int write = 1; + + LOG_DEBUG("address: 0x%8.8x, count: 0x%8.8x", address, count); + + if (target->state != TARGET_HALTED) + { + LOG_WARNING("target not halted"); + return ERROR_TARGET_NOT_HALTED; + } + + /* check alignment */ + if (address & 0x3u) + return ERROR_TARGET_UNALIGNED_ACCESS; + + /* Get memory for block write handler */ + retval = target_alloc_working_area(target, MIPS32_FASTDATA_HANDLER_SIZE, &source); + if (retval != ERROR_OK) + { + LOG_WARNING("No working area available, falling back to non-bulk write"); + return mips_m4k_write_memory(target, address, 4, count, buffer); + } + + /* TAP data register is loaded LSB first (little endian) */ + if (target->endianness == TARGET_BIG_ENDIAN) + { + uint32_t i, t32; + for(i = 0; i < (count * 4); i += 4) + { + t32 = be_to_h_u32((uint8_t *) &buffer[i]); + h_u32_to_le(&buffer[i], t32); + } + } + + retval = mips32_pracc_fastdata_xfer(ejtag_info, source, write, address, count, (uint32_t*) buffer); + + if (source) + target_free_working_area(target, source); + + return retval; } int mips_m4k_checksum_memory(struct target *target, uint32_t address, uint32_t size, uint32_t *checksum)