X-Git-Url: https://review.openocd.org/gitweb?a=blobdiff_plain;f=src%2Ftarget%2Fmips_ejtag.h;h=aa890d2b5ecfeb32d447f6bceab60f0b7ff3aa4f;hb=b1256894598296b54a1827e7ac797ad1c60a0b18;hp=2f62f2bebbed9bdbc8010155db105ae6887944c3;hpb=70738bd75dbc122e380ff3288542ac4e73700eed;p=openocd.git diff --git a/src/target/mips_ejtag.h b/src/target/mips_ejtag.h index 2f62f2bebb..aa890d2b5e 100644 --- a/src/target/mips_ejtag.h +++ b/src/target/mips_ejtag.h @@ -40,6 +40,17 @@ #define EJTAG_INST_TCBDATA 0x12 #define EJTAG_INST_BYPASS 0xFF +/* microchip PIC32MX specific instructions */ +#define MTAP_SW_MTAP 0x04 +#define MTAP_SW_ETAP 0x05 +#define MTAP_COMMAND 0x07 + +/* microchip specific cmds */ +#define MCHP_ASERT_RST 0xd1 +#define MCHP_DE_ASSERT_RST 0xd0 +#define MCHP_ERASE 0xfc +#define MCHP_STATUS 0x00 + /* ejtag control register bits ECR */ #define EJTAG_CTRL_TOF (1 << 1) #define EJTAG_CTRL_TIF (1 << 2) @@ -117,16 +128,18 @@ struct mips_ejtag uint32_t impcode; uint32_t idcode; uint32_t ejtag_ctrl; + int fast_access_save; }; -int mips_ejtag_set_instr(struct mips_ejtag *ejtag_info, - int new_instr, void *delete_me_and_submit_patch); +void mips_ejtag_set_instr(struct mips_ejtag *ejtag_info, + int new_instr); int mips_ejtag_enter_debug(struct mips_ejtag *ejtag_info); int mips_ejtag_exit_debug(struct mips_ejtag *ejtag_info); -int mips_ejtag_get_impcode(struct mips_ejtag *ejtag_info, uint32_t *impcode); int mips_ejtag_get_idcode(struct mips_ejtag *ejtag_info, uint32_t *idcode); int mips_ejtag_drscan_32(struct mips_ejtag *ejtag_info, uint32_t *data); -int mips_ejtag_fastdata_scan(struct mips_ejtag *ejtag_info, int write, uint32_t *data); +void mips_ejtag_drscan_8_out(struct mips_ejtag *ejtag_info, uint8_t data); +int mips_ejtag_drscan_8(struct mips_ejtag *ejtag_info, uint32_t *data); +int mips_ejtag_fastdata_scan(struct mips_ejtag *ejtag_info, int write_t, uint32_t *data); int mips_ejtag_init(struct mips_ejtag *ejtag_info); int mips_ejtag_config_step(struct mips_ejtag *ejtag_info, int enable_step);