X-Git-Url: https://review.openocd.org/gitweb?a=blobdiff_plain;f=src%2Ftarget%2Fmips32.h;h=bc88bc37c500d0384660812e8a3db59439da5fb3;hb=ae17ce23eb7bf4c0892c609f0a49daa8cd63d8c5;hp=049ce8f50e73afec1bff4484ec887582b2e9168d;hpb=6fd394811c23c623b9ad9aee5cffadbb4dc3e808;p=openocd.git

diff --git a/src/target/mips32.h b/src/target/mips32.h
index 049ce8f50e..bc88bc37c5 100644
--- a/src/target/mips32.h
+++ b/src/target/mips32.h
@@ -25,13 +25,13 @@
 
 #include "target.h"
 #include "register.h"
-#include "mips_ejtag.h"
 #include "mips32_pracc.h"
 
+
 #define MIPS32_COMMON_MAGIC		0xB320B320
 
 /* offsets into mips32 core register cache */
-enum 
+enum
 {
 	MIPS32_PC = 37,
 	MIPS32NUMCOREREGS
@@ -41,18 +41,18 @@ typedef struct mips32_comparator_s
 {
 	int used;
 	//int type;
-	u32 bp_value;
-	u32 reg_address;
+	uint32_t bp_value;
+	uint32_t reg_address;
 } mips32_comparator_t;
 
 typedef struct mips32_common_s
 {
-	u32 common_magic;
+	uint32_t common_magic;
 	void *arch_info;
 	reg_cache_t *core_cache;
 	mips_ejtag_t ejtag_info;
-	u32 core_regs[MIPS32NUMCOREREGS];
-	
+	uint32_t core_regs[MIPS32NUMCOREREGS];
+
 	int bp_scanned;
 	int num_inst_bpoints;
 	int num_data_bpoints;
@@ -60,7 +60,7 @@ typedef struct mips32_common_s
 	int num_data_bpoints_avail;
 	mips32_comparator_t *inst_break_list;
 	mips32_comparator_t *data_break_list;
-	
+
 	/* register cache to processor synchronization */
 	int (*read_core_reg)(struct target_s *target, int num);
 	int (*write_core_reg)(struct target_s *target, int num);
@@ -68,8 +68,8 @@ typedef struct mips32_common_s
 
 typedef struct mips32_core_reg_s
 {
-	u32 num;
-	target_t *target;
+	uint32_t num;
+	struct target_s *target;
 	mips32_common_t *mips32_common;
 } mips32_core_reg_t;
 
@@ -94,9 +94,9 @@ typedef struct mips32_core_reg_s
 #define MIPS32_COP0_MF	0x00
 #define MIPS32_COP0_MT	0x04
 
-#define MIPS32_R_INST(opcode, rs, rt, rd, shamt, funct)	(((opcode)<<26) |((rs)<<21)|((rt)<<16)|((rd)<<11)| ((shamt)<<6) | (funct))
-#define MIPS32_I_INST(opcode, rs, rt, immd)	(((opcode)<<26) |((rs)<<21)|((rt)<<16)|(immd))
-#define MIPS32_J_INST(opcode, addr)	(((opcode)<<26) |(addr))
+#define MIPS32_R_INST(opcode, rs, rt, rd, shamt, funct)	(((opcode) << 26) |((rs) << 21) | ((rt) << 16) | ((rd) << 11)| ((shamt) << 6) | (funct))
+#define MIPS32_I_INST(opcode, rs, rt, immd)	(((opcode) << 26) |((rs) << 21) | ((rt) << 16) | (immd))
+#define MIPS32_J_INST(opcode, addr)	(((opcode) << 26) |(addr))
 
 #define MIPS32_NOP					0
 #define MIPS32_ADDI(tar, src, val)	MIPS32_I_INST(MIPS32_OP_ADDI, src, tar, val)
@@ -129,8 +129,9 @@ extern int mips32_init_arch_info(target_t *target, mips32_common_t *mips32, jtag
 extern int mips32_restore_context(target_t *target);
 extern int mips32_save_context(target_t *target);
 extern reg_cache_t *mips32_build_reg_cache(target_t *target);
-extern int mips32_run_algorithm(struct target_s *target, int num_mem_params, mem_param_t *mem_params, int num_reg_params, reg_param_t *reg_params, u32 entry_point, u32 exit_point, int timeout_ms, void *arch_info);
+extern int mips32_run_algorithm(struct target_s *target, int num_mem_params, mem_param_t *mem_params, int num_reg_params, reg_param_t *reg_params, uint32_t entry_point, uint32_t exit_point, int timeout_ms, void *arch_info);
 extern int mips32_configure_break_unit(struct target_s *target);
+extern int mips32_enable_interrupts(struct target_s *target, int enable);
 extern int mips32_examine(struct target_s *target);
 
 extern int mips32_register_commands(struct command_context_s *cmd_ctx);