X-Git-Url: https://review.openocd.org/gitweb?a=blobdiff_plain;f=src%2Ftarget%2Fmips32.h;h=98186aff93cf507e8432ca15d14f31b8b428d5a8;hb=75c706cc043183d98592dbe3c6f170d627849d0f;hp=005798d5d259a305a2fa6130af8b9f6698e06e54;hpb=3885ab5a5af7ece410ce3eeb1059da3ea950436a;p=openocd.git

diff --git a/src/target/mips32.h b/src/target/mips32.h
index 005798d5d2..98186aff93 100644
--- a/src/target/mips32.h
+++ b/src/target/mips32.h
@@ -23,9 +23,8 @@
 #ifndef MIPS32_H
 #define MIPS32_H
 
-#include "target.h"
-#include "register.h"
-#include "mips32_pracc.h"
+#include <target/target.h>
+#include <target/mips32_pracc.h>
 
 
 #define MIPS32_COMMON_MAGIC		0xB320B320
@@ -37,20 +36,20 @@ enum
 	MIPS32NUMCOREREGS
 };
 
-typedef struct mips32_comparator_s
+struct mips32_comparator
 {
 	int used;
 	//int type;
 	uint32_t bp_value;
 	uint32_t reg_address;
-} mips32_comparator_t;
+};
 
-typedef struct mips32_common_s
+struct mips32_common
 {
 	uint32_t common_magic;
 	void *arch_info;
-	reg_cache_t *core_cache;
-	mips_ejtag_t ejtag_info;
+	struct reg_cache *core_cache;
+	struct mips_ejtag ejtag_info;
 	uint32_t core_regs[MIPS32NUMCOREREGS];
 
 	int bp_scanned;
@@ -58,20 +57,20 @@ typedef struct mips32_common_s
 	int num_data_bpoints;
 	int num_inst_bpoints_avail;
 	int num_data_bpoints_avail;
-	mips32_comparator_t *inst_break_list;
-	mips32_comparator_t *data_break_list;
+	struct mips32_comparator *inst_break_list;
+	struct mips32_comparator *data_break_list;
 
 	/* register cache to processor synchronization */
-	int (*read_core_reg)(struct target_s *target, int num);
-	int (*write_core_reg)(struct target_s *target, int num);
-} mips32_common_t;
+	int (*read_core_reg)(struct target *target, int num);
+	int (*write_core_reg)(struct target *target, int num);
+};
 
-typedef struct mips32_core_reg_s
+struct mips32_core_reg
 {
 	uint32_t num;
-	struct target_s *target;
-	mips32_common_t *mips32_common;
-} mips32_core_reg_t;
+	struct target *target;
+	struct mips32_common *mips32_common;
+};
 
 #define MIPS32_OP_BEQ	0x04
 #define MIPS32_OP_BNE	0x05
@@ -124,32 +123,31 @@ typedef struct mips32_core_reg_s
 #define MIPS32_SDBBP				0x7000003F
 #define MIPS16_SDBBP 				0xE801
 
-int mips32_arch_state(struct target_s *target);
+int mips32_arch_state(struct target *target);
 
-int mips32_init_arch_info(target_t *target,
-		mips32_common_t *mips32, jtag_tap_t *tap);
+int mips32_init_arch_info(struct target *target,
+		struct mips32_common *mips32, struct jtag_tap *tap);
 
-int mips32_restore_context(target_t *target);
-int mips32_save_context(target_t *target);
+int mips32_restore_context(struct target *target);
+int mips32_save_context(struct target *target);
 
-reg_cache_t *mips32_build_reg_cache(target_t *target);
+struct reg_cache *mips32_build_reg_cache(struct target *target);
 
-int mips32_run_algorithm(struct target_s *target,
-		int num_mem_params, mem_param_t *mem_params,
-		int num_reg_params, reg_param_t *reg_params,
+int mips32_run_algorithm(struct target *target,
+		int num_mem_params, struct mem_param *mem_params,
+		int num_reg_params, struct reg_param *reg_params,
 		uint32_t entry_point, uint32_t exit_point,
 		int timeout_ms, void *arch_info);
 
-int mips32_configure_break_unit(struct target_s *target);
+int mips32_configure_break_unit(struct target *target);
 
-int mips32_enable_interrupts(struct target_s *target, int enable);
+int mips32_enable_interrupts(struct target *target, int enable);
 
-int mips32_examine(struct target_s *target);
+int mips32_examine(struct target *target);
 
-int mips32_register_commands(struct command_context_s *cmd_ctx);
+int mips32_register_commands(struct command_context *cmd_ctx);
 
-int mips32_invalidate_core_regs(target_t *target);
-int mips32_get_gdb_reg_list(target_t *target,
-		reg_t **reg_list[], int *reg_list_size);
+int mips32_get_gdb_reg_list(struct target *target,
+		struct reg **reg_list[], int *reg_list_size);
 
 #endif	/*MIPS32_H*/