X-Git-Url: https://review.openocd.org/gitweb?a=blobdiff_plain;f=src%2Ftarget%2Fmips32.c;h=cec45499a8564468047a69cca849ce54fa0288c4;hb=e17d1d4dc870155010422095272d8a6c16435451;hp=11f39fea881d6b1c43944c8a97236314c38eddf8;hpb=bc1340cf0b9aa28c03d1b07c54b6e0bf4a483351;p=openocd.git diff --git a/src/target/mips32.c b/src/target/mips32.c index 11f39fea88..cec45499a8 100644 --- a/src/target/mips32.c +++ b/src/target/mips32.c @@ -21,9 +21,7 @@ * GNU General Public License for more details. * * * * You should have received a copy of the GNU General Public License * - * along with this program; if not, write to the * - * Free Software Foundation, Inc., * - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. * + * along with this program. If not, see . * ***************************************************************************/ #ifdef HAVE_CONFIG_H @@ -36,70 +34,137 @@ #include "register.h" static const char *mips_isa_strings[] = { - "MIPS32", "MIPS16e" + "MIPS32", "MIPS16" }; +#define MIPS32_GDB_DUMMY_FP_REG 1 + +/* + * GDB registers + * based on gdb-7.6.2/gdb/features/mips-{fpu,cp0,cpu}.xml + */ static const struct { unsigned id; const char *name; -} mips32_regs[MIPS32NUMCOREREGS] = { - { 0, "zero", }, - { 1, "at", }, - { 2, "v0", }, - { 3, "v1", }, - { 4, "a0", }, - { 5, "a1", }, - { 6, "a2", }, - { 7, "a3", }, - { 8, "t0", }, - { 9, "t1", }, - { 10, "t2", }, - { 11, "t3", }, - { 12, "t4", }, - { 13, "t5", }, - { 14, "t6", }, - { 15, "t7", }, - { 16, "s0", }, - { 17, "s1", }, - { 18, "s2", }, - { 19, "s3", }, - { 20, "s4", }, - { 21, "s5", }, - { 22, "s6", }, - { 23, "s7", }, - { 24, "t8", }, - { 25, "t9", }, - { 26, "k0", }, - { 27, "k1", }, - { 28, "gp", }, - { 29, "sp", }, - { 30, "fp", }, - { 31, "ra", }, - - { 32, "status", }, - { 33, "lo", }, - { 34, "hi", }, - { 35, "badvaddr", }, - { 36, "cause", }, - { 37, "pc" }, + enum reg_type type; + const char *group; + const char *feature; + int flag; +} mips32_regs[] = { + { 0, "r0", REG_TYPE_INT, NULL, "org.gnu.gdb.mips.cpu", 0 }, + { 1, "r1", REG_TYPE_INT, NULL, "org.gnu.gdb.mips.cpu", 0 }, + { 2, "r2", REG_TYPE_INT, NULL, "org.gnu.gdb.mips.cpu", 0 }, + { 3, "r3", REG_TYPE_INT, NULL, "org.gnu.gdb.mips.cpu", 0 }, + { 4, "r4", REG_TYPE_INT, NULL, "org.gnu.gdb.mips.cpu", 0 }, + { 5, "r5", REG_TYPE_INT, NULL, "org.gnu.gdb.mips.cpu", 0 }, + { 6, "r6", REG_TYPE_INT, NULL, "org.gnu.gdb.mips.cpu", 0 }, + { 7, "r7", REG_TYPE_INT, NULL, "org.gnu.gdb.mips.cpu", 0 }, + { 8, "r8", REG_TYPE_INT, NULL, "org.gnu.gdb.mips.cpu", 0 }, + { 9, "r9", REG_TYPE_INT, NULL, "org.gnu.gdb.mips.cpu", 0 }, + { 10, "r10", REG_TYPE_INT, NULL, "org.gnu.gdb.mips.cpu", 0 }, + { 11, "r11", REG_TYPE_INT, NULL, "org.gnu.gdb.mips.cpu", 0 }, + { 12, "r12", REG_TYPE_INT, NULL, "org.gnu.gdb.mips.cpu", 0 }, + { 13, "r13", REG_TYPE_INT, NULL, "org.gnu.gdb.mips.cpu", 0 }, + { 14, "r14", REG_TYPE_INT, NULL, "org.gnu.gdb.mips.cpu", 0 }, + { 15, "r15", REG_TYPE_INT, NULL, "org.gnu.gdb.mips.cpu", 0 }, + { 16, "r16", REG_TYPE_INT, NULL, "org.gnu.gdb.mips.cpu", 0 }, + { 17, "r17", REG_TYPE_INT, NULL, "org.gnu.gdb.mips.cpu", 0 }, + { 18, "r18", REG_TYPE_INT, NULL, "org.gnu.gdb.mips.cpu", 0 }, + { 19, "r19", REG_TYPE_INT, NULL, "org.gnu.gdb.mips.cpu", 0 }, + { 20, "r20", REG_TYPE_INT, NULL, "org.gnu.gdb.mips.cpu", 0 }, + { 21, "r21", REG_TYPE_INT, NULL, "org.gnu.gdb.mips.cpu", 0 }, + { 22, "r22", REG_TYPE_INT, NULL, "org.gnu.gdb.mips.cpu", 0 }, + { 23, "r23", REG_TYPE_INT, NULL, "org.gnu.gdb.mips.cpu", 0 }, + { 24, "r24", REG_TYPE_INT, NULL, "org.gnu.gdb.mips.cpu", 0 }, + { 25, "r25", REG_TYPE_INT, NULL, "org.gnu.gdb.mips.cpu", 0 }, + { 26, "r26", REG_TYPE_INT, NULL, "org.gnu.gdb.mips.cpu", 0 }, + { 27, "r27", REG_TYPE_INT, NULL, "org.gnu.gdb.mips.cpu", 0 }, + { 28, "r28", REG_TYPE_INT, NULL, "org.gnu.gdb.mips.cpu", 0 }, + { 29, "r29", REG_TYPE_INT, NULL, "org.gnu.gdb.mips.cpu", 0 }, + { 30, "r30", REG_TYPE_INT, NULL, "org.gnu.gdb.mips.cpu", 0 }, + { 31, "r31", REG_TYPE_INT, NULL, "org.gnu.gdb.mips.cpu", 0 }, + { 32, "status", REG_TYPE_INT, NULL, "org.gnu.gdb.mips.cp0", 0 }, + { 33, "lo", REG_TYPE_INT, NULL, "org.gnu.gdb.mips.cpu", 0 }, + { 34, "hi", REG_TYPE_INT, NULL, "org.gnu.gdb.mips.cpu", 0 }, + { 35, "badvaddr", REG_TYPE_INT, NULL, "org.gnu.gdb.mips.cp0", 0 }, + { 36, "cause", REG_TYPE_INT, NULL, "org.gnu.gdb.mips.cp0", 0 }, + { 37, "pc", REG_TYPE_INT, NULL, "org.gnu.gdb.mips.cpu", 0 }, + + { 38, "f0", REG_TYPE_IEEE_SINGLE, NULL, + "org.gnu.gdb.mips.fpu", MIPS32_GDB_DUMMY_FP_REG }, + { 39, "f1", REG_TYPE_IEEE_SINGLE, NULL, + "org.gnu.gdb.mips.fpu", MIPS32_GDB_DUMMY_FP_REG }, + { 40, "f2", REG_TYPE_IEEE_SINGLE, NULL, + "org.gnu.gdb.mips.fpu", MIPS32_GDB_DUMMY_FP_REG }, + { 41, "f3", REG_TYPE_IEEE_SINGLE, NULL, + "org.gnu.gdb.mips.fpu", MIPS32_GDB_DUMMY_FP_REG }, + { 42, "f4", REG_TYPE_IEEE_SINGLE, NULL, + "org.gnu.gdb.mips.fpu", MIPS32_GDB_DUMMY_FP_REG }, + { 43, "f5", REG_TYPE_IEEE_SINGLE, NULL, + "org.gnu.gdb.mips.fpu", MIPS32_GDB_DUMMY_FP_REG }, + { 44, "f6", REG_TYPE_IEEE_SINGLE, NULL, + "org.gnu.gdb.mips.fpu", MIPS32_GDB_DUMMY_FP_REG }, + { 45, "f7", REG_TYPE_IEEE_SINGLE, NULL, + "org.gnu.gdb.mips.fpu", MIPS32_GDB_DUMMY_FP_REG }, + { 46, "f8", REG_TYPE_IEEE_SINGLE, NULL, + "org.gnu.gdb.mips.fpu", MIPS32_GDB_DUMMY_FP_REG }, + { 47, "f9", REG_TYPE_IEEE_SINGLE, NULL, + "org.gnu.gdb.mips.fpu", MIPS32_GDB_DUMMY_FP_REG }, + { 48, "f10", REG_TYPE_IEEE_SINGLE, NULL, + "org.gnu.gdb.mips.fpu", MIPS32_GDB_DUMMY_FP_REG }, + { 49, "f11", REG_TYPE_IEEE_SINGLE, NULL, + "org.gnu.gdb.mips.fpu", MIPS32_GDB_DUMMY_FP_REG }, + { 50, "f12", REG_TYPE_IEEE_SINGLE, NULL, + "org.gnu.gdb.mips.fpu", MIPS32_GDB_DUMMY_FP_REG }, + { 51, "f13", REG_TYPE_IEEE_SINGLE, NULL, + "org.gnu.gdb.mips.fpu", MIPS32_GDB_DUMMY_FP_REG }, + { 52, "f14", REG_TYPE_IEEE_SINGLE, NULL, + "org.gnu.gdb.mips.fpu", MIPS32_GDB_DUMMY_FP_REG }, + { 53, "f15", REG_TYPE_IEEE_SINGLE, NULL, + "org.gnu.gdb.mips.fpu", MIPS32_GDB_DUMMY_FP_REG }, + { 54, "f16", REG_TYPE_IEEE_SINGLE, NULL, + "org.gnu.gdb.mips.fpu", MIPS32_GDB_DUMMY_FP_REG }, + { 55, "f17", REG_TYPE_IEEE_SINGLE, NULL, + "org.gnu.gdb.mips.fpu", MIPS32_GDB_DUMMY_FP_REG }, + { 56, "f18", REG_TYPE_IEEE_SINGLE, NULL, + "org.gnu.gdb.mips.fpu", MIPS32_GDB_DUMMY_FP_REG }, + { 57, "f19", REG_TYPE_IEEE_SINGLE, NULL, + "org.gnu.gdb.mips.fpu", MIPS32_GDB_DUMMY_FP_REG }, + { 58, "f20", REG_TYPE_IEEE_SINGLE, NULL, + "org.gnu.gdb.mips.fpu", MIPS32_GDB_DUMMY_FP_REG }, + { 59, "f21", REG_TYPE_IEEE_SINGLE, NULL, + "org.gnu.gdb.mips.fpu", MIPS32_GDB_DUMMY_FP_REG }, + { 60, "f22", REG_TYPE_IEEE_SINGLE, NULL, + "org.gnu.gdb.mips.fpu", MIPS32_GDB_DUMMY_FP_REG }, + { 61, "f23", REG_TYPE_IEEE_SINGLE, NULL, + "org.gnu.gdb.mips.fpu", MIPS32_GDB_DUMMY_FP_REG }, + { 62, "f24", REG_TYPE_IEEE_SINGLE, NULL, + "org.gnu.gdb.mips.fpu", MIPS32_GDB_DUMMY_FP_REG }, + { 63, "f25", REG_TYPE_IEEE_SINGLE, NULL, + "org.gnu.gdb.mips.fpu", MIPS32_GDB_DUMMY_FP_REG }, + { 64, "f26", REG_TYPE_IEEE_SINGLE, NULL, + "org.gnu.gdb.mips.fpu", MIPS32_GDB_DUMMY_FP_REG }, + { 65, "f27", REG_TYPE_IEEE_SINGLE, NULL, + "org.gnu.gdb.mips.fpu", MIPS32_GDB_DUMMY_FP_REG }, + { 66, "f28", REG_TYPE_IEEE_SINGLE, NULL, + "org.gnu.gdb.mips.fpu", MIPS32_GDB_DUMMY_FP_REG }, + { 67, "f29", REG_TYPE_IEEE_SINGLE, NULL, + "org.gnu.gdb.mips.fpu", MIPS32_GDB_DUMMY_FP_REG }, + { 68, "f30", REG_TYPE_IEEE_SINGLE, NULL, + "org.gnu.gdb.mips.fpu", MIPS32_GDB_DUMMY_FP_REG }, + { 69, "f31", REG_TYPE_IEEE_SINGLE, NULL, + "org.gnu.gdb.mips.fpu", MIPS32_GDB_DUMMY_FP_REG }, + { 70, "fcsr", REG_TYPE_INT, "float", + "org.gnu.gdb.mips.fpu", MIPS32_GDB_DUMMY_FP_REG }, + { 71, "fir", REG_TYPE_INT, "float", + "org.gnu.gdb.mips.fpu", MIPS32_GDB_DUMMY_FP_REG }, }; -/* number of mips dummy fp regs fp0 - fp31 + fsr and fir - * we also add 18 unknown registers to handle gdb requests */ -#define MIPS32NUMFPREGS (34 + 18) +#define MIPS32_NUM_REGS ARRAY_SIZE(mips32_regs) static uint8_t mips32_gdb_dummy_fp_value[] = {0, 0, 0, 0}; -static struct reg mips32_gdb_dummy_fp_reg = { - .name = "GDB dummy floating-point register", - .value = mips32_gdb_dummy_fp_value, - .dirty = 0, - .valid = 1, - .size = 32, - .arch_info = NULL, -}; - static int mips32_get_core_reg(struct reg *reg) { int retval; @@ -131,14 +196,14 @@ static int mips32_set_core_reg(struct reg *reg, uint8_t *buf) return ERROR_OK; } -static int mips32_read_core_reg(struct target *target, int num) +static int mips32_read_core_reg(struct target *target, unsigned int num) { uint32_t reg_value; /* get pointers to arch-specific information */ struct mips32_common *mips32 = target_to_mips32(target); - if ((num < 0) || (num >= MIPS32NUMCOREREGS)) + if (num >= MIPS32_NUM_REGS) return ERROR_COMMAND_SYNTAX_ERROR; reg_value = mips32->core_regs[num]; @@ -149,14 +214,14 @@ static int mips32_read_core_reg(struct target *target, int num) return ERROR_OK; } -static int mips32_write_core_reg(struct target *target, int num) +static int mips32_write_core_reg(struct target *target, unsigned int num) { uint32_t reg_value; /* get pointers to arch-specific information */ struct mips32_common *mips32 = target_to_mips32(target); - if ((num < 0) || (num >= MIPS32NUMCOREREGS)) + if (num >= MIPS32_NUM_REGS) return ERROR_COMMAND_SYNTAX_ERROR; reg_value = buf_get_u32(mips32->core_cache->reg_list[num].value, 0, 32); @@ -173,25 +238,21 @@ int mips32_get_gdb_reg_list(struct target *target, struct reg **reg_list[], { /* get pointers to arch-specific information */ struct mips32_common *mips32 = target_to_mips32(target); - int i; + unsigned int i; /* include floating point registers */ - *reg_list_size = MIPS32NUMCOREREGS + MIPS32NUMFPREGS; + *reg_list_size = MIPS32_NUM_REGS; *reg_list = malloc(sizeof(struct reg *) * (*reg_list_size)); - for (i = 0; i < MIPS32NUMCOREREGS; i++) + for (i = 0; i < MIPS32_NUM_REGS; i++) (*reg_list)[i] = &mips32->core_cache->reg_list[i]; - /* add dummy floating points regs */ - for (i = MIPS32NUMCOREREGS; i < (MIPS32NUMCOREREGS + MIPS32NUMFPREGS); i++) - (*reg_list)[i] = &mips32_gdb_dummy_fp_reg; - return ERROR_OK; } int mips32_save_context(struct target *target) { - int i; + unsigned int i; /* get pointers to arch-specific information */ struct mips32_common *mips32 = target_to_mips32(target); @@ -200,7 +261,7 @@ int mips32_save_context(struct target *target) /* read core registers */ mips32_pracc_read_regs(ejtag_info, mips32->core_regs); - for (i = 0; i < MIPS32NUMCOREREGS; i++) { + for (i = 0; i < MIPS32_NUM_REGS; i++) { if (!mips32->core_cache->reg_list[i].valid) mips32->read_core_reg(target, i); } @@ -210,13 +271,13 @@ int mips32_save_context(struct target *target) int mips32_restore_context(struct target *target) { - int i; + unsigned int i; /* get pointers to arch-specific information */ struct mips32_common *mips32 = target_to_mips32(target); struct mips_ejtag *ejtag_info = &mips32->ejtag_info; - for (i = 0; i < MIPS32NUMCOREREGS; i++) { + for (i = 0; i < MIPS32_NUM_REGS; i++) { if (mips32->core_cache->reg_list[i].dirty) mips32->write_core_reg(target, i); } @@ -249,15 +310,14 @@ struct reg_cache *mips32_build_reg_cache(struct target *target) /* get pointers to arch-specific information */ struct mips32_common *mips32 = target_to_mips32(target); - int num_regs = MIPS32NUMCOREREGS; + int num_regs = MIPS32_NUM_REGS; struct reg_cache **cache_p = register_get_last_cache_p(&target->reg_cache); struct reg_cache *cache = malloc(sizeof(struct reg_cache)); - struct reg *reg_list = malloc(sizeof(struct reg) * num_regs); + struct reg *reg_list = calloc(num_regs, sizeof(struct reg)); struct mips32_core_reg *arch_info = malloc(sizeof(struct mips32_core_reg) * num_regs); + struct reg_feature *feature; int i; - register_init_dummy(&mips32_gdb_dummy_fp_reg); - /* Build the process context cache */ cache->name = "mips32 registers"; cache->next = NULL; @@ -273,11 +333,38 @@ struct reg_cache *mips32_build_reg_cache(struct target *target) reg_list[i].name = mips32_regs[i].name; reg_list[i].size = 32; - reg_list[i].value = calloc(1, 4); + + if (mips32_regs[i].flag == MIPS32_GDB_DUMMY_FP_REG) { + reg_list[i].value = mips32_gdb_dummy_fp_value; + reg_list[i].valid = 1; + reg_list[i].arch_info = NULL; + register_init_dummy(®_list[i]); + } else { + reg_list[i].value = calloc(1, 4); + reg_list[i].valid = 0; + reg_list[i].type = &mips32_reg_type; + reg_list[i].arch_info = &arch_info[i]; + + reg_list[i].reg_data_type = calloc(1, sizeof(struct reg_data_type)); + if (reg_list[i].reg_data_type) + reg_list[i].reg_data_type->type = mips32_regs[i].type; + else + LOG_ERROR("unable to allocate reg type list"); + } + reg_list[i].dirty = 0; - reg_list[i].valid = 0; - reg_list[i].type = &mips32_reg_type; - reg_list[i].arch_info = &arch_info[i]; + + reg_list[i].group = mips32_regs[i].group; + reg_list[i].number = i; + reg_list[i].exist = true; + reg_list[i].caller_save = true; /* gdb defaults to true */ + + feature = calloc(1, sizeof(struct reg_feature)); + if (feature) { + feature->name = mips32_regs[i].feature; + reg_list[i].feature = feature; + } else + LOG_ERROR("unable to allocate feature list"); } return cache; @@ -289,7 +376,7 @@ int mips32_init_arch_info(struct target *target, struct mips32_common *mips32, s mips32->common_magic = MIPS32_COMMON_MAGIC; mips32->fast_data_area = NULL; - /* has breakpoint/watchpint unit been scanned */ + /* has breakpoint/watchpoint unit been scanned */ mips32->bp_scanned = 0; mips32->data_break_list = NULL; @@ -297,15 +384,15 @@ int mips32_init_arch_info(struct target *target, struct mips32_common *mips32, s mips32->read_core_reg = mips32_read_core_reg; mips32->write_core_reg = mips32_write_core_reg; - mips32->ejtag_info.scan_delay = 2000000; /* Initial default value */ + mips32->ejtag_info.scan_delay = MIPS32_SCAN_DELAY_LEGACY_MODE; /* Initial default value */ mips32->ejtag_info.mode = 0; /* Initial default value */ return ERROR_OK; } /* run to exit point. return error if exit point was not reached. */ -static int mips32_run_and_wait(struct target *target, uint32_t entry_point, - int timeout_ms, uint32_t exit_point, struct mips32_common *mips32) +static int mips32_run_and_wait(struct target *target, target_addr_t entry_point, + int timeout_ms, target_addr_t exit_point, struct mips32_common *mips32) { uint32_t pc; int retval; @@ -338,15 +425,14 @@ static int mips32_run_and_wait(struct target *target, uint32_t entry_point, int mips32_run_algorithm(struct target *target, int num_mem_params, struct mem_param *mem_params, int num_reg_params, - struct reg_param *reg_params, uint32_t entry_point, - uint32_t exit_point, int timeout_ms, void *arch_info) + struct reg_param *reg_params, target_addr_t entry_point, + target_addr_t exit_point, int timeout_ms, void *arch_info) { struct mips32_common *mips32 = target_to_mips32(target); struct mips32_algorithm *mips32_algorithm_info = arch_info; enum mips32_isa_mode isa_mode = mips32->isa_mode; - uint32_t context[MIPS32NUMCOREREGS]; - int i; + uint32_t context[MIPS32_NUM_REGS]; int retval = ERROR_OK; LOG_DEBUG("Running algorithm"); @@ -365,20 +451,20 @@ int mips32_run_algorithm(struct target *target, int num_mem_params, } /* refresh core register cache */ - for (i = 0; i < MIPS32NUMCOREREGS; i++) { + for (unsigned int i = 0; i < MIPS32_NUM_REGS; i++) { if (!mips32->core_cache->reg_list[i].valid) mips32->read_core_reg(target, i); context[i] = buf_get_u32(mips32->core_cache->reg_list[i].value, 0, 32); } - for (i = 0; i < num_mem_params; i++) { + for (int i = 0; i < num_mem_params; i++) { retval = target_write_buffer(target, mem_params[i].address, mem_params[i].size, mem_params[i].value); if (retval != ERROR_OK) return retval; } - for (i = 0; i < num_reg_params; i++) { + for (int i = 0; i < num_reg_params; i++) { struct reg *reg = register_get_by_name(mips32->core_cache, reg_params[i].reg_name, 0); if (!reg) { @@ -402,7 +488,7 @@ int mips32_run_algorithm(struct target *target, int num_mem_params, if (retval != ERROR_OK) return retval; - for (i = 0; i < num_mem_params; i++) { + for (int i = 0; i < num_mem_params; i++) { if (mem_params[i].direction != PARAM_OUT) { retval = target_read_buffer(target, mem_params[i].address, mem_params[i].size, mem_params[i].value); @@ -411,7 +497,7 @@ int mips32_run_algorithm(struct target *target, int num_mem_params, } } - for (i = 0; i < num_reg_params; i++) { + for (int i = 0; i < num_reg_params; i++) { if (reg_params[i].direction != PARAM_OUT) { struct reg *reg = register_get_by_name(mips32->core_cache, reg_params[i].reg_name, 0); if (!reg) { @@ -430,7 +516,7 @@ int mips32_run_algorithm(struct target *target, int num_mem_params, } /* restore everything we saved before */ - for (i = 0; i < MIPS32NUMCOREREGS; i++) { + for (unsigned int i = 0; i < MIPS32_NUM_REGS; i++) { uint32_t regvalue; regvalue = buf_get_u32(mips32->core_cache->reg_list[i].value, 0, 32); if (regvalue != context[i]) { @@ -536,26 +622,36 @@ int mips32_configure_break_unit(struct target *target) if (retval != ERROR_OK) return retval; - /* EJTAG 2.0 does not specify EJTAG_DCR_IB and EJTAG_DCR_DB bits, - * assume IB and DB registers are always present. */ - if (ejtag_info->ejtag_version == EJTAG_VERSION_20) - dcr |= EJTAG_DCR_IB | EJTAG_DCR_DB; + /* EJTAG 2.0 defines IB and DB bits in IMP instead of DCR. */ + if (ejtag_info->ejtag_version == EJTAG_VERSION_20) { + ejtag_info->debug_caps = dcr & EJTAG_DCR_ENM; + if (!(ejtag_info->impcode & EJTAG_V20_IMP_NOIB)) + ejtag_info->debug_caps |= EJTAG_DCR_IB; + if (!(ejtag_info->impcode & EJTAG_V20_IMP_NODB)) + ejtag_info->debug_caps |= EJTAG_DCR_DB; + } else + /* keep debug caps for later use */ + ejtag_info->debug_caps = dcr & (EJTAG_DCR_ENM + | EJTAG_DCR_IB | EJTAG_DCR_DB); + - if (dcr & EJTAG_DCR_IB) { + if (ejtag_info->debug_caps & EJTAG_DCR_IB) { retval = mips32_configure_ibs(target); if (retval != ERROR_OK) return retval; } - if (dcr & EJTAG_DCR_DB) { + if (ejtag_info->debug_caps & EJTAG_DCR_DB) { retval = mips32_configure_dbs(target); if (retval != ERROR_OK) return retval; } /* check if target endianness settings matches debug control register */ - if (((dcr & EJTAG_DCR_ENM) && (target->endianness == TARGET_LITTLE_ENDIAN)) || - (!(dcr & EJTAG_DCR_ENM) && (target->endianness == TARGET_BIG_ENDIAN))) + if (((ejtag_info->debug_caps & EJTAG_DCR_ENM) + && (target->endianness == TARGET_LITTLE_ENDIAN)) || + (!(ejtag_info->debug_caps & EJTAG_DCR_ENM) + && (target->endianness == TARGET_BIG_ENDIAN))) LOG_WARNING("DCR endianness settings does not match target settings"); LOG_DEBUG("DCR 0x%" PRIx32 " numinst %i numdata %i", dcr, mips32->num_inst_bpoints, @@ -600,16 +696,14 @@ int mips32_enable_interrupts(struct target *target, int enable) return ERROR_OK; } -int mips32_checksum_memory(struct target *target, uint32_t address, +int mips32_checksum_memory(struct target *target, target_addr_t address, uint32_t count, uint32_t *checksum) { struct working_area *crc_algorithm; struct reg_param reg_params[2]; struct mips32_algorithm mips32_info; - int retval; - uint32_t i; - /* see contib/loaders/checksum/mips32.s for src */ + /* see contrib/loaders/checksum/mips32.s for src */ static const uint32_t mips_crc_code[] = { 0x248C0000, /* addiu $t4, $a0, 0 */ @@ -644,50 +738,46 @@ int mips32_checksum_memory(struct target *target, uint32_t address, if (target_alloc_working_area(target, sizeof(mips_crc_code), &crc_algorithm) != ERROR_OK) return ERROR_TARGET_RESOURCE_NOT_AVAILABLE; - /* convert flash writing code into a buffer in target endianness */ - for (i = 0; i < ARRAY_SIZE(mips_crc_code); i++) - target_write_u32(target, crc_algorithm->address + i*sizeof(uint32_t), mips_crc_code[i]); + /* convert mips crc code into a buffer in target endianness */ + uint8_t mips_crc_code_8[sizeof(mips_crc_code)]; + target_buffer_set_u32_array(target, mips_crc_code_8, + ARRAY_SIZE(mips_crc_code), mips_crc_code); + + target_write_buffer(target, crc_algorithm->address, sizeof(mips_crc_code), mips_crc_code_8); mips32_info.common_magic = MIPS32_COMMON_MAGIC; mips32_info.isa_mode = MIPS32_ISA_MIPS32; - init_reg_param(®_params[0], "a0", 32, PARAM_IN_OUT); + init_reg_param(®_params[0], "r4", 32, PARAM_IN_OUT); buf_set_u32(reg_params[0].value, 0, 32, address); - init_reg_param(®_params[1], "a1", 32, PARAM_OUT); + init_reg_param(®_params[1], "r5", 32, PARAM_OUT); buf_set_u32(reg_params[1].value, 0, 32, count); int timeout = 20000 * (1 + (count / (1024 * 1024))); - retval = target_run_algorithm(target, 0, NULL, 2, reg_params, - crc_algorithm->address, crc_algorithm->address + (sizeof(mips_crc_code)-4), timeout, + int retval = target_run_algorithm(target, 0, NULL, 2, reg_params, + crc_algorithm->address, crc_algorithm->address + (sizeof(mips_crc_code) - 4), timeout, &mips32_info); - if (retval != ERROR_OK) { - destroy_reg_param(®_params[0]); - destroy_reg_param(®_params[1]); - target_free_working_area(target, crc_algorithm); - return retval; - } - *checksum = buf_get_u32(reg_params[0].value, 0, 32); + if (retval == ERROR_OK) + *checksum = buf_get_u32(reg_params[0].value, 0, 32); destroy_reg_param(®_params[0]); destroy_reg_param(®_params[1]); target_free_working_area(target, crc_algorithm); - return ERROR_OK; + return retval; } -/** Checks whether a memory region is zeroed. */ +/** Checks whether a memory region is erased. */ int mips32_blank_check_memory(struct target *target, - uint32_t address, uint32_t count, uint32_t *blank) + target_addr_t address, uint32_t count, uint32_t *blank, uint8_t erased_value) { struct working_area *erase_check_algorithm; struct reg_param reg_params[3]; struct mips32_algorithm mips32_info; - int retval; - uint32_t i; static const uint32_t erase_check_code[] = { /* nbyte: */ @@ -699,41 +789,42 @@ int mips32_blank_check_memory(struct target *target, 0x7000003F /* sdbbp */ }; + if (erased_value != 0xff) { + LOG_ERROR("Erase value 0x%02" PRIx8 " not yet supported for MIPS32", + erased_value); + return ERROR_FAIL; + } + /* make sure we have a working area */ if (target_alloc_working_area(target, sizeof(erase_check_code), &erase_check_algorithm) != ERROR_OK) return ERROR_TARGET_RESOURCE_NOT_AVAILABLE; - /* convert flash writing code into a buffer in target endianness */ - for (i = 0; i < ARRAY_SIZE(erase_check_code); i++) { - target_write_u32(target, erase_check_algorithm->address + i*sizeof(uint32_t), - erase_check_code[i]); - } + /* convert erase check code into a buffer in target endianness */ + uint8_t erase_check_code_8[sizeof(erase_check_code)]; + target_buffer_set_u32_array(target, erase_check_code_8, + ARRAY_SIZE(erase_check_code), erase_check_code); + + target_write_buffer(target, erase_check_algorithm->address, sizeof(erase_check_code), erase_check_code_8); mips32_info.common_magic = MIPS32_COMMON_MAGIC; mips32_info.isa_mode = MIPS32_ISA_MIPS32; - init_reg_param(®_params[0], "a0", 32, PARAM_OUT); + init_reg_param(®_params[0], "r4", 32, PARAM_OUT); buf_set_u32(reg_params[0].value, 0, 32, address); - init_reg_param(®_params[1], "a1", 32, PARAM_OUT); + init_reg_param(®_params[1], "r5", 32, PARAM_OUT); buf_set_u32(reg_params[1].value, 0, 32, count); - init_reg_param(®_params[2], "a2", 32, PARAM_IN_OUT); - buf_set_u32(reg_params[2].value, 0, 32, 0xff); + init_reg_param(®_params[2], "r6", 32, PARAM_IN_OUT); + buf_set_u32(reg_params[2].value, 0, 32, erased_value); - retval = target_run_algorithm(target, 0, NULL, 3, reg_params, + int retval = target_run_algorithm(target, 0, NULL, 3, reg_params, erase_check_algorithm->address, - erase_check_algorithm->address + (sizeof(erase_check_code)-4), + erase_check_algorithm->address + (sizeof(erase_check_code) - 4), 10000, &mips32_info); - if (retval != ERROR_OK) { - destroy_reg_param(®_params[0]); - destroy_reg_param(®_params[1]); - destroy_reg_param(®_params[2]); - target_free_working_area(target, erase_check_algorithm); - return retval; - } - *blank = buf_get_u32(reg_params[2].value, 0, 32); + if (retval == ERROR_OK) + *blank = buf_get_u32(reg_params[2].value, 0, 32); destroy_reg_param(®_params[0]); destroy_reg_param(®_params[1]); @@ -741,7 +832,7 @@ int mips32_blank_check_memory(struct target *target, target_free_working_area(target, erase_check_algorithm); - return ERROR_OK; + return retval; } static int mips32_verify_pointer(struct command_context *cmd_ctx, @@ -826,7 +917,7 @@ COMMAND_HANDLER(mips32_handle_scan_delay_command) return ERROR_COMMAND_SYNTAX_ERROR; command_print(CMD_CTX, "scan delay: %d nsec", ejtag_info->scan_delay); - if (ejtag_info->scan_delay >= 2000000) { + if (ejtag_info->scan_delay >= MIPS32_SCAN_DELAY_LEGACY_MODE) { ejtag_info->mode = 0; command_print(CMD_CTX, "running in legacy mode"); } else {