X-Git-Url: https://review.openocd.org/gitweb?a=blobdiff_plain;f=src%2Ftarget%2Fferoceon.c;h=e1dc068642f70b75dde83ffe3d6d2820585f3bb9;hb=ab33bdd46c3bb3acdb3f1b1f09a0e1a9393ef798;hp=b9339bf3c37e6c110d90ee31c7229d9ecc5019c6;hpb=53d605e12c3765aeedabf2bfe0c5cc338dc95d5a;p=openocd.git diff --git a/src/target/feroceon.c b/src/target/feroceon.c index b9339bf3c3..e1dc068642 100644 --- a/src/target/feroceon.c +++ b/src/target/feroceon.c @@ -1,5 +1,5 @@ /*************************************************************************** - * Copyright (C) 2008 by Marvell Semiconductors, Inc. * + * Copyright (C) 2008-2009 by Marvell Semiconductors, Inc. * * Written by Nicolas Pitre * * * * Copyright (C) 2008 by Hongtao Zheng * @@ -22,10 +22,10 @@ ***************************************************************************/ /* - * Marvell Feroceon support, including Orion and Kirkwood SOCs. + * Marvell Feroceon/Dragonite support. * - * The Feroceon core mimics the ARM926 ICE interface with the following - * differences: + * The Feroceon core, as found in the Orion and Kirkwood SoCs amongst others, + * mimics the ARM926 ICE interface with the following differences: * * - the MOE (method of entry) reporting is not implemented * @@ -43,6 +43,9 @@ * * - the DCC channel is half duplex (only one FIFO for both directions) with * seemingly no proper flow control. + * + * The Dragonite core is the non-mmu version based on the ARM966 model, and + * it shares the above issues as well. */ #ifdef HAVE_CONFIG_H @@ -50,15 +53,9 @@ #endif #include "arm926ejs.h" +#include "arm966e.h" #include "target_type.h" - -int feroceon_examine(struct target_s *target); -int feroceon_target_create(struct target_s *target, Jim_Interp *interp); -int feroceon_bulk_write_memory(target_t *target, uint32_t address, uint32_t count, uint8_t *buffer); -int feroceon_init_target(struct command_context_s *cmd_ctx, struct target_s *target); -int feroceon_quit(void); - int feroceon_assert_reset(target_t *target) { armv4_5_common_t *armv4_5 = target->arch_info; @@ -72,46 +69,6 @@ int feroceon_assert_reset(target_t *target) return arm7_9_assert_reset(target); } -target_type_t feroceon_target = -{ - .name = "feroceon", - - .poll = arm7_9_poll, - .arch_state = arm926ejs_arch_state, - - .target_request_data = arm7_9_target_request_data, - - .halt = arm7_9_halt, - .resume = arm7_9_resume, - .step = arm7_9_step, - - .assert_reset = feroceon_assert_reset, - .deassert_reset = arm7_9_deassert_reset, - .soft_reset_halt = arm926ejs_soft_reset_halt, - - .get_gdb_reg_list = armv4_5_get_gdb_reg_list, - - .read_memory = arm7_9_read_memory, - .write_memory = arm926ejs_write_memory, - .bulk_write_memory = feroceon_bulk_write_memory, - .checksum_memory = arm7_9_checksum_memory, - .blank_check_memory = arm7_9_blank_check_memory, - - .run_algorithm = armv4_5_run_algorithm, - - .add_breakpoint = arm7_9_add_breakpoint, - .remove_breakpoint = arm7_9_remove_breakpoint, - .add_watchpoint = arm7_9_add_watchpoint, - .remove_watchpoint = arm7_9_remove_watchpoint, - - .register_commands = arm926ejs_register_commands, - .target_create = feroceon_target_create, - .init_target = feroceon_init_target, - .examine = feroceon_examine, - .quit = feroceon_quit -}; - - int feroceon_dummy_clock_out(arm_jtag_t *jtag_info, uint32_t instr) { scan_field_t fields[3]; @@ -132,32 +89,17 @@ int feroceon_dummy_clock_out(arm_jtag_t *jtag_info, uint32_t instr) fields[0].tap = jtag_info->tap; fields[0].num_bits = 32; fields[0].out_value = out_buf; - fields[0].in_value = NULL; - - - - fields[1].tap = jtag_info->tap; fields[1].num_bits = 3; fields[1].out_value = &sysspeed_buf; - fields[1].in_value = NULL; - - - - fields[2].tap = jtag_info->tap; fields[2].num_bits = 32; fields[2].out_value = instr_buf; - fields[2].in_value = NULL; - - - - jtag_add_dr_scan(3, fields, jtag_get_end_state()); @@ -393,7 +335,6 @@ void feroceon_branch_resume_thumb(target_t *target) arm_jtag_t *jtag_info = &arm7_9->jtag_info; uint32_t r0 = buf_get_u32(armv4_5->core_cache->reg_list[0].value, 0, 32); uint32_t pc = buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32); - (void)(r0); // use R0... arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0); arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0); @@ -409,7 +350,7 @@ void feroceon_branch_resume_thumb(target_t *target) arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0); arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0); - arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, pc, NULL, 0); + arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, r0, NULL, 0); arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0); arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0); @@ -606,9 +547,20 @@ int feroceon_bulk_write_memory(target_t *target, uint32_t address, uint32_t coun buffer += 4; } - target_halt(target); - while (target->state != TARGET_HALTED) - target_poll(target); + retval = target_halt(target); + if (retval == ERROR_OK) + retval = target_wait_state(target, TARGET_HALTED, 500); + if (retval == ERROR_OK) { + uint32_t endaddress = + buf_get_u32(armv4_5->core_cache->reg_list[0].value, 0, 32); + if (endaddress != address + count*4) { + LOG_ERROR("DCC write failed," + " expected end address 0x%08" PRIx32 + " got 0x%0" PRIx32 "", + address + count*4, endaddress); + retval = ERROR_FAIL; + } + } /* restore target state */ for (i = 0; i <= 5; i++) @@ -622,7 +574,7 @@ int feroceon_bulk_write_memory(target_t *target, uint32_t address, uint32_t coun armv4_5->core_cache->reg_list[15].dirty = 1; armv4_5->core_state = core_state; - return ERROR_OK; + return retval; } int feroceon_init_target(struct command_context_s *cmd_ctx, struct target_s *target) @@ -631,21 +583,10 @@ int feroceon_init_target(struct command_context_s *cmd_ctx, struct target_s *tar return ERROR_OK; } -int feroceon_quit(void) +void feroceon_common_setup(struct target_s *target) { - return ERROR_OK; -} - -int feroceon_target_create(struct target_s *target, Jim_Interp *interp) -{ - armv4_5_common_t *armv4_5; - arm7_9_common_t *arm7_9; - arm926ejs_common_t *arm926ejs = calloc(1,sizeof(arm926ejs_common_t)); - - arm926ejs_init_arch_info(target, arm926ejs, target->tap); - - armv4_5 = target->arch_info; - arm7_9 = armv4_5->arch_info; + armv4_5_common_t *armv4_5 = target->arch_info; + arm7_9_common_t *arm7_9 = armv4_5->arch_info; /* override some insn sequence functions */ arm7_9->change_to_arm = feroceon_change_to_arm; @@ -665,10 +606,6 @@ int feroceon_target_create(struct target_s *target, Jim_Interp *interp) /* MOE is not implemented */ arm7_9->examine_debug_reason = feroceon_examine_debug_reason; - /* the standard ARM926 methods don't always work (don't ask...) */ - arm926ejs->read_cp15 = feroceon_read_cp15; - arm926ejs->write_cp15 = feroceon_write_cp15; - /* Note: asserting DBGRQ might not win over the undef exception. If that happens then just use "arm7_9 dbgrq disable". */ arm7_9->use_dbgrq = 1; @@ -677,6 +614,28 @@ int feroceon_target_create(struct target_s *target, Jim_Interp *interp) /* only one working comparator */ arm7_9->wp_available_max = 1; arm7_9->wp1_used_default = -1; +} + +int feroceon_target_create(struct target_s *target, Jim_Interp *interp) +{ + arm926ejs_common_t *arm926ejs = calloc(1,sizeof(arm926ejs_common_t)); + + arm926ejs_init_arch_info(target, arm926ejs, target->tap); + feroceon_common_setup(target); + + /* the standard ARM926 methods don't always work (don't ask...) */ + arm926ejs->read_cp15 = feroceon_read_cp15; + arm926ejs->write_cp15 = feroceon_write_cp15; + + return ERROR_OK; +} + +int dragonite_target_create(struct target_s *target, Jim_Interp *interp) +{ + arm966e_common_t *arm966e = calloc(1,sizeof(arm966e_common_t)); + + arm966e_init_arch_info(target, arm966e, target->tap); + feroceon_common_setup(target); return ERROR_OK; } @@ -714,3 +673,80 @@ int feroceon_examine(struct target_s *target) return ERROR_OK; } + +target_type_t feroceon_target = +{ + .name = "feroceon", + + .poll = arm7_9_poll, + .arch_state = arm926ejs_arch_state, + + .target_request_data = arm7_9_target_request_data, + + .halt = arm7_9_halt, + .resume = arm7_9_resume, + .step = arm7_9_step, + + .assert_reset = feroceon_assert_reset, + .deassert_reset = arm7_9_deassert_reset, + .soft_reset_halt = arm926ejs_soft_reset_halt, + + .get_gdb_reg_list = armv4_5_get_gdb_reg_list, + + .read_memory = arm7_9_read_memory, + .write_memory = arm926ejs_write_memory, + .bulk_write_memory = feroceon_bulk_write_memory, + .checksum_memory = arm7_9_checksum_memory, + .blank_check_memory = arm7_9_blank_check_memory, + + .run_algorithm = armv4_5_run_algorithm, + + .add_breakpoint = arm7_9_add_breakpoint, + .remove_breakpoint = arm7_9_remove_breakpoint, + .add_watchpoint = arm7_9_add_watchpoint, + .remove_watchpoint = arm7_9_remove_watchpoint, + + .register_commands = arm926ejs_register_commands, + .target_create = feroceon_target_create, + .init_target = feroceon_init_target, + .examine = feroceon_examine, +}; + +target_type_t dragonite_target = +{ + .name = "dragonite", + + .poll = arm7_9_poll, + .arch_state = armv4_5_arch_state, + + .target_request_data = arm7_9_target_request_data, + + .halt = arm7_9_halt, + .resume = arm7_9_resume, + .step = arm7_9_step, + + .assert_reset = feroceon_assert_reset, + .deassert_reset = arm7_9_deassert_reset, + .soft_reset_halt = arm7_9_soft_reset_halt, + + .get_gdb_reg_list = armv4_5_get_gdb_reg_list, + + .read_memory = arm7_9_read_memory, + .write_memory = arm7_9_write_memory, + .bulk_write_memory = feroceon_bulk_write_memory, + .checksum_memory = arm7_9_checksum_memory, + .blank_check_memory = arm7_9_blank_check_memory, + + .run_algorithm = armv4_5_run_algorithm, + + .add_breakpoint = arm7_9_add_breakpoint, + .remove_breakpoint = arm7_9_remove_breakpoint, + .add_watchpoint = arm7_9_add_watchpoint, + .remove_watchpoint = arm7_9_remove_watchpoint, + + .register_commands = arm966e_register_commands, + .target_create = dragonite_target_create, + .init_target = feroceon_init_target, + .examine = feroceon_examine, +}; +