X-Git-Url: https://review.openocd.org/gitweb?a=blobdiff_plain;f=src%2Ftarget%2Fferoceon.c;h=19ed0cd50d80f135da63390e64d93a52bb9573dc;hb=bc088b302bd0bb43cc9097a9f0b2e7369b0e04e2;hp=cf034c428963a9011f3e077e9a41d5629a1d66a6;hpb=af949b2531d2a8863d077025db40cbb170d13a63;p=openocd.git

diff --git a/src/target/feroceon.c b/src/target/feroceon.c
index cf034c4289..19ed0cd50d 100644
--- a/src/target/feroceon.c
+++ b/src/target/feroceon.c
@@ -55,8 +55,11 @@
 #include "arm926ejs.h"
 #include "arm966e.h"
 #include "target_type.h"
+#include "register.h"
+#include "arm_opcodes.h"
 
-int feroceon_assert_reset(target_t *target)
+
+int feroceon_assert_reset(struct target *target)
 {
 	struct arm *armv4_5 = target->arch_info;
 	struct arm7_9_common *arm7_9 = armv4_5->arch_info;
@@ -108,7 +111,7 @@ int feroceon_dummy_clock_out(struct arm_jtag *jtag_info, uint32_t instr)
 	return ERROR_OK;
 }
 
-void feroceon_change_to_arm(target_t *target, uint32_t *r0, uint32_t *pc)
+void feroceon_change_to_arm(struct target *target, uint32_t *r0, uint32_t *pc)
 {
 	struct arm *armv4_5 = target->arch_info;
 	struct arm7_9_common *arm7_9 = armv4_5->arch_info;
@@ -154,7 +157,7 @@ void feroceon_change_to_arm(target_t *target, uint32_t *r0, uint32_t *pc)
 	*pc -= (12 + 4);
 }
 
-void feroceon_read_core_regs(target_t *target, uint32_t mask, uint32_t* core_regs[16])
+void feroceon_read_core_regs(struct target *target, uint32_t mask, uint32_t* core_regs[16])
 {
 	int i;
 	struct arm *armv4_5 = target->arch_info;
@@ -173,7 +176,7 @@ void feroceon_read_core_regs(target_t *target, uint32_t mask, uint32_t* core_reg
 	arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
 }
 
-void feroceon_read_core_regs_target_buffer(target_t *target, uint32_t mask, void* buffer, int size)
+void feroceon_read_core_regs_target_buffer(struct target *target, uint32_t mask, void* buffer, int size)
 {
 	int i;
 	struct arm *armv4_5 = target->arch_info;
@@ -210,7 +213,7 @@ void feroceon_read_core_regs_target_buffer(target_t *target, uint32_t mask, void
 	arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
 }
 
-void feroceon_read_xpsr(target_t *target, uint32_t *xpsr, int spsr)
+void feroceon_read_xpsr(struct target *target, uint32_t *xpsr, int spsr)
 {
 	struct arm *armv4_5 = target->arch_info;
 	struct arm7_9_common *arm7_9 = armv4_5->arch_info;
@@ -233,7 +236,7 @@ void feroceon_read_xpsr(target_t *target, uint32_t *xpsr, int spsr)
 	arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
 }
 
-void feroceon_write_xpsr(target_t *target, uint32_t xpsr, int spsr)
+void feroceon_write_xpsr(struct target *target, uint32_t xpsr, int spsr)
 {
 	struct arm *armv4_5 = target->arch_info;
 	struct arm7_9_common *arm7_9 = armv4_5->arch_info;
@@ -274,7 +277,7 @@ void feroceon_write_xpsr(target_t *target, uint32_t xpsr, int spsr)
 	arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
 }
 
-void feroceon_write_xpsr_im8(target_t *target, uint8_t xpsr_im, int rot, int spsr)
+void feroceon_write_xpsr_im8(struct target *target, uint8_t xpsr_im, int rot, int spsr)
 {
 	struct arm *armv4_5 = target->arch_info;
 	struct arm7_9_common *arm7_9 = armv4_5->arch_info;
@@ -291,7 +294,7 @@ void feroceon_write_xpsr_im8(target_t *target, uint8_t xpsr_im, int rot, int sps
 	arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
 }
 
-void feroceon_write_core_regs(target_t *target, uint32_t mask, uint32_t core_regs[16])
+void feroceon_write_core_regs(struct target *target, uint32_t mask, uint32_t core_regs[16])
 {
 	int i;
 	struct arm *armv4_5 = target->arch_info;
@@ -311,7 +314,7 @@ void feroceon_write_core_regs(target_t *target, uint32_t mask, uint32_t core_reg
 	arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
 }
 
-void feroceon_branch_resume(target_t *target)
+void feroceon_branch_resume(struct target *target)
 {
 	struct arm *armv4_5 = target->arch_info;
 	struct arm7_9_common *arm7_9 = armv4_5->arch_info;
@@ -326,7 +329,7 @@ void feroceon_branch_resume(target_t *target)
 	arm7_9->need_bypass_before_restart = 1;
 }
 
-void feroceon_branch_resume_thumb(target_t *target)
+void feroceon_branch_resume_thumb(struct target *target)
 {
 	LOG_DEBUG("-");
 
@@ -361,7 +364,7 @@ void feroceon_branch_resume_thumb(target_t *target)
 	arm7_9->need_bypass_before_restart = 1;
 }
 
-int feroceon_read_cp15(target_t *target, uint32_t op1, uint32_t op2, uint32_t CRn, uint32_t CRm, uint32_t *value)
+int feroceon_read_cp15(struct target *target, uint32_t op1, uint32_t op2, uint32_t CRn, uint32_t CRm, uint32_t *value)
 {
 	struct arm *armv4_5 = target->arch_info;
 	struct arm7_9_common *arm7_9 = armv4_5->arch_info;
@@ -383,7 +386,7 @@ int feroceon_read_cp15(target_t *target, uint32_t op1, uint32_t op2, uint32_t CR
 	return jtag_execute_queue();
 }
 
-int feroceon_write_cp15(target_t *target, uint32_t op1, uint32_t op2, uint32_t CRn, uint32_t CRm, uint32_t value)
+int feroceon_write_cp15(struct target *target, uint32_t op1, uint32_t op2, uint32_t CRn, uint32_t CRm, uint32_t value)
 {
 	struct arm *armv4_5 = target->arch_info;
 	struct arm7_9_common *arm7_9 = armv4_5->arch_info;
@@ -402,17 +405,17 @@ int feroceon_write_cp15(target_t *target, uint32_t op1, uint32_t op2, uint32_t C
 	return arm7_9_execute_sys_speed(target);
 }
 
-void feroceon_set_dbgrq(target_t *target)
+void feroceon_set_dbgrq(struct target *target)
 {
 	struct arm *armv4_5 = target->arch_info;
 	struct arm7_9_common *arm7_9 = armv4_5->arch_info;
-	reg_t *dbg_ctrl = &arm7_9->eice_cache->reg_list[EICE_DBG_CTRL];
+	struct reg *dbg_ctrl = &arm7_9->eice_cache->reg_list[EICE_DBG_CTRL];
 
 	buf_set_u32(dbg_ctrl->value, 0, 8, 2);
 	embeddedice_store_reg(dbg_ctrl);
 }
 
-void feroceon_enable_single_step(target_t *target, uint32_t next_pc)
+void feroceon_enable_single_step(struct target *target, uint32_t next_pc)
 {
 	struct arm *armv4_5 = target->arch_info;
 	struct arm7_9_common *arm7_9 = armv4_5->arch_info;
@@ -425,7 +428,7 @@ void feroceon_enable_single_step(target_t *target, uint32_t next_pc)
 	embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_MASK], 0xf7);
 }
 
-void feroceon_disable_single_step(target_t *target)
+void feroceon_disable_single_step(struct target *target)
 {
 	struct arm *armv4_5 = target->arch_info;
 	struct arm7_9_common *arm7_9 = armv4_5->arch_info;
@@ -437,7 +440,7 @@ void feroceon_disable_single_step(target_t *target)
 	embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE]);
 }
 
-int feroceon_examine_debug_reason(target_t *target)
+int feroceon_examine_debug_reason(struct target *target)
 {
 	/* the MOE is not implemented */
 	if (target->debug_reason != DBG_REASON_SINGLESTEP)
@@ -448,12 +451,12 @@ int feroceon_examine_debug_reason(target_t *target)
 	return ERROR_OK;
 }
 
-int feroceon_bulk_write_memory(target_t *target, uint32_t address, uint32_t count, uint8_t *buffer)
+int feroceon_bulk_write_memory(struct target *target, uint32_t address, uint32_t count, uint8_t *buffer)
 {
 	int retval;
 	struct arm *armv4_5 = target->arch_info;
 	struct arm7_9_common *arm7_9 = armv4_5->arch_info;
-	enum armv4_5_state core_state = armv4_5->core_state;
+	enum arm_state core_state = armv4_5->core_state;
 	uint32_t x, flip, shift, save[7];
 	uint32_t i;
 
@@ -522,7 +525,7 @@ int feroceon_bulk_write_memory(target_t *target, uint32_t address, uint32_t coun
 	buf_set_u32(armv4_5->core_cache->reg_list[0].value, 0, 32, address);
 	armv4_5->core_cache->reg_list[0].valid = 1;
 	armv4_5->core_cache->reg_list[0].dirty = 1;
-	armv4_5->core_state = ARMV4_5_STATE_ARM;
+	armv4_5->core_state = ARM_STATE_ARM;
 
 	embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_COMMS_DATA], 0);
 	arm7_9_resume(target, 0, arm7_9->dcc_working_area->address, 1, 1);
@@ -577,13 +580,13 @@ int feroceon_bulk_write_memory(target_t *target, uint32_t address, uint32_t coun
 	return retval;
 }
 
-int feroceon_init_target(struct command_context_s *cmd_ctx, struct target_s *target)
+int feroceon_init_target(struct command_context *cmd_ctx, struct target *target)
 {
 	arm9tdmi_init_target(cmd_ctx, target);
 	return ERROR_OK;
 }
 
-void feroceon_common_setup(struct target_s *target)
+void feroceon_common_setup(struct target *target)
 {
 	struct arm *armv4_5 = target->arch_info;
 	struct arm7_9_common *arm7_9 = armv4_5->arch_info;
@@ -616,7 +619,7 @@ void feroceon_common_setup(struct target_s *target)
 	arm7_9->wp1_used_default = -1;
 }
 
-int feroceon_target_create(struct target_s *target, Jim_Interp *interp)
+int feroceon_target_create(struct target *target, Jim_Interp *interp)
 {
 	struct arm926ejs_common *arm926ejs = calloc(1,sizeof(struct arm926ejs_common));
 
@@ -630,7 +633,7 @@ int feroceon_target_create(struct target_s *target, Jim_Interp *interp)
 	return ERROR_OK;
 }
 
-int dragonite_target_create(struct target_s *target, Jim_Interp *interp)
+int dragonite_target_create(struct target *target, Jim_Interp *interp)
 {
 	struct arm966e_common *arm966e = calloc(1,sizeof(struct arm966e_common));
 
@@ -640,13 +643,13 @@ int dragonite_target_create(struct target_s *target, Jim_Interp *interp)
 	return ERROR_OK;
 }
 
-int feroceon_examine(struct target_s *target)
+int feroceon_examine(struct target *target)
 {
 	struct arm *armv4_5;
 	struct arm7_9_common *arm7_9;
 	int retval;
 
-	retval = arm9tdmi_examine(target);
+	retval = arm7_9_examine(target);
 	if (retval != ERROR_OK)
 		return retval;
 
@@ -674,7 +677,7 @@ int feroceon_examine(struct target_s *target)
 	return ERROR_OK;
 }
 
-target_type_t feroceon_target =
+struct target_type feroceon_target =
 {
 	.name = "feroceon",
 
@@ -691,13 +694,14 @@ target_type_t feroceon_target =
 	.deassert_reset = arm7_9_deassert_reset,
 	.soft_reset_halt = arm926ejs_soft_reset_halt,
 
-	.get_gdb_reg_list = armv4_5_get_gdb_reg_list,
+	.get_gdb_reg_list = arm_get_gdb_reg_list,
 
 	.read_memory = arm7_9_read_memory,
 	.write_memory = arm926ejs_write_memory,
 	.bulk_write_memory = feroceon_bulk_write_memory,
-	.checksum_memory = arm7_9_checksum_memory,
-	.blank_check_memory = arm7_9_blank_check_memory,
+
+	.checksum_memory = arm_checksum_memory,
+	.blank_check_memory = arm_blank_check_memory,
 
 	.run_algorithm = armv4_5_run_algorithm,
 
@@ -706,18 +710,18 @@ target_type_t feroceon_target =
 	.add_watchpoint = arm7_9_add_watchpoint,
 	.remove_watchpoint = arm7_9_remove_watchpoint,
 
-	.register_commands = arm926ejs_register_commands,
+	.commands = arm926ejs_command_handlers,
 	.target_create = feroceon_target_create,
 	.init_target = feroceon_init_target,
 	.examine = feroceon_examine,
 };
 
-target_type_t dragonite_target =
+struct target_type dragonite_target =
 {
 	.name = "dragonite",
 
 	.poll = arm7_9_poll,
-	.arch_state = armv4_5_arch_state,
+	.arch_state = arm_arch_state,
 
 	.target_request_data = arm7_9_target_request_data,
 
@@ -729,13 +733,14 @@ target_type_t dragonite_target =
 	.deassert_reset = arm7_9_deassert_reset,
 	.soft_reset_halt = arm7_9_soft_reset_halt,
 
-	.get_gdb_reg_list = armv4_5_get_gdb_reg_list,
+	.get_gdb_reg_list = arm_get_gdb_reg_list,
 
 	.read_memory = arm7_9_read_memory,
 	.write_memory = arm7_9_write_memory,
 	.bulk_write_memory = feroceon_bulk_write_memory,
-	.checksum_memory = arm7_9_checksum_memory,
-	.blank_check_memory = arm7_9_blank_check_memory,
+
+	.checksum_memory = arm_checksum_memory,
+	.blank_check_memory = arm_blank_check_memory,
 
 	.run_algorithm = armv4_5_run_algorithm,
 
@@ -744,7 +749,7 @@ target_type_t dragonite_target =
 	.add_watchpoint = arm7_9_add_watchpoint,
 	.remove_watchpoint = arm7_9_remove_watchpoint,
 
-	.register_commands = arm966e_register_commands,
+	.commands = arm966e_command_handlers,
 	.target_create = dragonite_target_create,
 	.init_target = feroceon_init_target,
 	.examine = feroceon_examine,