X-Git-Url: https://review.openocd.org/gitweb?a=blobdiff_plain;f=src%2Ftarget%2Fferoceon.c;h=03a5afcaefd32d25e6087aed8f892f206e5dfd75;hb=2280ddeea5fd82554696f1caa97f7a485a035da4;hp=536b678b3f5f923b2804f60c0a882f66134e5296;hpb=bd4377194e6842b3d50b76827c45a90019d7bb46;p=openocd.git diff --git a/src/target/feroceon.c b/src/target/feroceon.c index 536b678b3f..03a5afcaef 100644 --- a/src/target/feroceon.c +++ b/src/target/feroceon.c @@ -1,5 +1,5 @@ /*************************************************************************** - * Copyright (C) 2008 by Marvell Semiconductors, Inc. * + * Copyright (C) 2008-2009 by Marvell Semiconductors, Inc. * * Written by Nicolas Pitre * * * * Copyright (C) 2008 by Hongtao Zheng * @@ -22,10 +22,10 @@ ***************************************************************************/ /* - * Marvell Feroceon support, including Orion and Kirkwood SOCs. + * Marvell Feroceon/Dragonite support. * - * The Feroceon core mimics the ARM926 ICE interface with the following - * differences: + * The Feroceon core, as found in the Orion and Kirkwood SoCs amongst others, + * mimics the ARM926 ICE interface with the following differences: * * - the MOE (method of entry) reporting is not implemented * @@ -43,6 +43,9 @@ * * - the DCC channel is half duplex (only one FIFO for both directions) with * seemingly no proper flow control. + * + * The Dragonite core is the non-mmu version based on the ARM966 model, and + * it shares the above issues as well. */ #ifdef HAVE_CONFIG_H @@ -50,19 +53,13 @@ #endif #include "arm926ejs.h" +#include "arm966e.h" #include "target_type.h" - -int feroceon_examine(struct target_s *target); -int feroceon_target_create(struct target_s *target, Jim_Interp *interp); -int feroceon_bulk_write_memory(target_t *target, uint32_t address, uint32_t count, uint8_t *buffer); -int feroceon_init_target(struct command_context_s *cmd_ctx, struct target_s *target); -int feroceon_quit(void); - -int feroceon_assert_reset(target_t *target) +int feroceon_assert_reset(struct target *target) { - armv4_5_common_t *armv4_5 = target->arch_info; - arm7_9_common_t *arm7_9 = armv4_5->arch_info; + struct arm *armv4_5 = target->arch_info; + struct arm7_9_common *arm7_9 = armv4_5->arch_info; int ud = arm7_9->use_dbgrq; arm7_9->use_dbgrq = 0; @@ -72,49 +69,9 @@ int feroceon_assert_reset(target_t *target) return arm7_9_assert_reset(target); } -target_type_t feroceon_target = +int feroceon_dummy_clock_out(struct arm_jtag *jtag_info, uint32_t instr) { - .name = "feroceon", - - .poll = arm7_9_poll, - .arch_state = arm926ejs_arch_state, - - .target_request_data = arm7_9_target_request_data, - - .halt = arm7_9_halt, - .resume = arm7_9_resume, - .step = arm7_9_step, - - .assert_reset = feroceon_assert_reset, - .deassert_reset = arm7_9_deassert_reset, - .soft_reset_halt = arm926ejs_soft_reset_halt, - - .get_gdb_reg_list = armv4_5_get_gdb_reg_list, - - .read_memory = arm7_9_read_memory, - .write_memory = arm926ejs_write_memory, - .bulk_write_memory = feroceon_bulk_write_memory, - .checksum_memory = arm7_9_checksum_memory, - .blank_check_memory = arm7_9_blank_check_memory, - - .run_algorithm = armv4_5_run_algorithm, - - .add_breakpoint = arm7_9_add_breakpoint, - .remove_breakpoint = arm7_9_remove_breakpoint, - .add_watchpoint = arm7_9_add_watchpoint, - .remove_watchpoint = arm7_9_remove_watchpoint, - - .register_commands = arm926ejs_register_commands, - .target_create = feroceon_target_create, - .init_target = feroceon_init_target, - .examine = feroceon_examine, - .quit = feroceon_quit -}; - - -int feroceon_dummy_clock_out(arm_jtag_t *jtag_info, uint32_t instr) -{ - scan_field_t fields[3]; + struct scan_field fields[3]; uint8_t out_buf[4]; uint8_t instr_buf[4]; uint8_t sysspeed_buf = 0x0; @@ -151,11 +108,11 @@ int feroceon_dummy_clock_out(arm_jtag_t *jtag_info, uint32_t instr) return ERROR_OK; } -void feroceon_change_to_arm(target_t *target, uint32_t *r0, uint32_t *pc) +void feroceon_change_to_arm(struct target *target, uint32_t *r0, uint32_t *pc) { - armv4_5_common_t *armv4_5 = target->arch_info; - arm7_9_common_t *arm7_9 = armv4_5->arch_info; - arm_jtag_t *jtag_info = &arm7_9->jtag_info; + struct arm *armv4_5 = target->arch_info; + struct arm7_9_common *arm7_9 = armv4_5->arch_info; + struct arm_jtag *jtag_info = &arm7_9->jtag_info; /* * save r0 before using it and put system in ARM state @@ -197,12 +154,12 @@ void feroceon_change_to_arm(target_t *target, uint32_t *r0, uint32_t *pc) *pc -= (12 + 4); } -void feroceon_read_core_regs(target_t *target, uint32_t mask, uint32_t* core_regs[16]) +void feroceon_read_core_regs(struct target *target, uint32_t mask, uint32_t* core_regs[16]) { int i; - armv4_5_common_t *armv4_5 = target->arch_info; - arm7_9_common_t *arm7_9 = armv4_5->arch_info; - arm_jtag_t *jtag_info = &arm7_9->jtag_info; + struct arm *armv4_5 = target->arch_info; + struct arm7_9_common *arm7_9 = armv4_5->arch_info; + struct arm_jtag *jtag_info = &arm7_9->jtag_info; arm9tdmi_clock_out(jtag_info, ARMV4_5_STMIA(0, mask & 0xffff, 0, 0), 0, NULL, 0); arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0); @@ -216,12 +173,12 @@ void feroceon_read_core_regs(target_t *target, uint32_t mask, uint32_t* core_reg arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0); } -void feroceon_read_core_regs_target_buffer(target_t *target, uint32_t mask, void* buffer, int size) +void feroceon_read_core_regs_target_buffer(struct target *target, uint32_t mask, void* buffer, int size) { int i; - armv4_5_common_t *armv4_5 = target->arch_info; - arm7_9_common_t *arm7_9 = armv4_5->arch_info; - arm_jtag_t *jtag_info = &arm7_9->jtag_info; + struct arm *armv4_5 = target->arch_info; + struct arm7_9_common *arm7_9 = armv4_5->arch_info; + struct arm_jtag *jtag_info = &arm7_9->jtag_info; int be = (target->endianness == TARGET_BIG_ENDIAN) ? 1 : 0; uint32_t *buf_u32 = buffer; uint16_t *buf_u16 = buffer; @@ -253,11 +210,11 @@ void feroceon_read_core_regs_target_buffer(target_t *target, uint32_t mask, void arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0); } -void feroceon_read_xpsr(target_t *target, uint32_t *xpsr, int spsr) +void feroceon_read_xpsr(struct target *target, uint32_t *xpsr, int spsr) { - armv4_5_common_t *armv4_5 = target->arch_info; - arm7_9_common_t *arm7_9 = armv4_5->arch_info; - arm_jtag_t *jtag_info = &arm7_9->jtag_info; + struct arm *armv4_5 = target->arch_info; + struct arm7_9_common *arm7_9 = armv4_5->arch_info; + struct arm_jtag *jtag_info = &arm7_9->jtag_info; arm9tdmi_clock_out(jtag_info, ARMV4_5_MRS(0, spsr & 1), 0, NULL, 0); arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0); @@ -276,11 +233,11 @@ void feroceon_read_xpsr(target_t *target, uint32_t *xpsr, int spsr) arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0); } -void feroceon_write_xpsr(target_t *target, uint32_t xpsr, int spsr) +void feroceon_write_xpsr(struct target *target, uint32_t xpsr, int spsr) { - armv4_5_common_t *armv4_5 = target->arch_info; - arm7_9_common_t *arm7_9 = armv4_5->arch_info; - arm_jtag_t *jtag_info = &arm7_9->jtag_info; + struct arm *armv4_5 = target->arch_info; + struct arm7_9_common *arm7_9 = armv4_5->arch_info; + struct arm_jtag *jtag_info = &arm7_9->jtag_info; LOG_DEBUG("xpsr: %8.8" PRIx32 ", spsr: %i", xpsr, spsr); @@ -317,11 +274,11 @@ void feroceon_write_xpsr(target_t *target, uint32_t xpsr, int spsr) arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0); } -void feroceon_write_xpsr_im8(target_t *target, uint8_t xpsr_im, int rot, int spsr) +void feroceon_write_xpsr_im8(struct target *target, uint8_t xpsr_im, int rot, int spsr) { - armv4_5_common_t *armv4_5 = target->arch_info; - arm7_9_common_t *arm7_9 = armv4_5->arch_info; - arm_jtag_t *jtag_info = &arm7_9->jtag_info; + struct arm *armv4_5 = target->arch_info; + struct arm7_9_common *arm7_9 = armv4_5->arch_info; + struct arm_jtag *jtag_info = &arm7_9->jtag_info; LOG_DEBUG("xpsr_im: %2.2x, rot: %i, spsr: %i", xpsr_im, rot, spsr); @@ -334,12 +291,12 @@ void feroceon_write_xpsr_im8(target_t *target, uint8_t xpsr_im, int rot, int sps arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0); } -void feroceon_write_core_regs(target_t *target, uint32_t mask, uint32_t core_regs[16]) +void feroceon_write_core_regs(struct target *target, uint32_t mask, uint32_t core_regs[16]) { int i; - armv4_5_common_t *armv4_5 = target->arch_info; - arm7_9_common_t *arm7_9 = armv4_5->arch_info; - arm_jtag_t *jtag_info = &arm7_9->jtag_info; + struct arm *armv4_5 = target->arch_info; + struct arm7_9_common *arm7_9 = armv4_5->arch_info; + struct arm_jtag *jtag_info = &arm7_9->jtag_info; arm9tdmi_clock_out(jtag_info, ARMV4_5_LDMIA(0, mask & 0xffff, 0, 0), 0, NULL, 0); arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0); @@ -354,11 +311,11 @@ void feroceon_write_core_regs(target_t *target, uint32_t mask, uint32_t core_reg arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0); } -void feroceon_branch_resume(target_t *target) +void feroceon_branch_resume(struct target *target) { - armv4_5_common_t *armv4_5 = target->arch_info; - arm7_9_common_t *arm7_9 = armv4_5->arch_info; - arm_jtag_t *jtag_info = &arm7_9->jtag_info; + struct arm *armv4_5 = target->arch_info; + struct arm7_9_common *arm7_9 = armv4_5->arch_info; + struct arm_jtag *jtag_info = &arm7_9->jtag_info; arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0); arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0); @@ -369,16 +326,15 @@ void feroceon_branch_resume(target_t *target) arm7_9->need_bypass_before_restart = 1; } -void feroceon_branch_resume_thumb(target_t *target) +void feroceon_branch_resume_thumb(struct target *target) { LOG_DEBUG("-"); - armv4_5_common_t *armv4_5 = target->arch_info; - arm7_9_common_t *arm7_9 = armv4_5->arch_info; - arm_jtag_t *jtag_info = &arm7_9->jtag_info; + struct arm *armv4_5 = target->arch_info; + struct arm7_9_common *arm7_9 = armv4_5->arch_info; + struct arm_jtag *jtag_info = &arm7_9->jtag_info; uint32_t r0 = buf_get_u32(armv4_5->core_cache->reg_list[0].value, 0, 32); uint32_t pc = buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32); - (void)(r0); // use R0... arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0); arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0); @@ -394,7 +350,7 @@ void feroceon_branch_resume_thumb(target_t *target) arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0); arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0); - arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, pc, NULL, 0); + arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, r0, NULL, 0); arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0); arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0); @@ -405,11 +361,11 @@ void feroceon_branch_resume_thumb(target_t *target) arm7_9->need_bypass_before_restart = 1; } -int feroceon_read_cp15(target_t *target, uint32_t op1, uint32_t op2, uint32_t CRn, uint32_t CRm, uint32_t *value) +int feroceon_read_cp15(struct target *target, uint32_t op1, uint32_t op2, uint32_t CRn, uint32_t CRm, uint32_t *value) { - armv4_5_common_t *armv4_5 = target->arch_info; - arm7_9_common_t *arm7_9 = armv4_5->arch_info; - arm_jtag_t *jtag_info = &arm7_9->jtag_info; + struct arm *armv4_5 = target->arch_info; + struct arm7_9_common *arm7_9 = armv4_5->arch_info; + struct arm_jtag *jtag_info = &arm7_9->jtag_info; int err; arm9tdmi_clock_out(jtag_info, ARMV4_5_MRC(15, op1, 0, CRn, CRm, op2), 0, NULL, 0); @@ -427,11 +383,11 @@ int feroceon_read_cp15(target_t *target, uint32_t op1, uint32_t op2, uint32_t CR return jtag_execute_queue(); } -int feroceon_write_cp15(target_t *target, uint32_t op1, uint32_t op2, uint32_t CRn, uint32_t CRm, uint32_t value) +int feroceon_write_cp15(struct target *target, uint32_t op1, uint32_t op2, uint32_t CRn, uint32_t CRm, uint32_t value) { - armv4_5_common_t *armv4_5 = target->arch_info; - arm7_9_common_t *arm7_9 = armv4_5->arch_info; - arm_jtag_t *jtag_info = &arm7_9->jtag_info; + struct arm *armv4_5 = target->arch_info; + struct arm7_9_common *arm7_9 = armv4_5->arch_info; + struct arm_jtag *jtag_info = &arm7_9->jtag_info; arm9tdmi_clock_out(jtag_info, ARMV4_5_LDMIA(0, 1, 0, 0), 0, NULL, 0); arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0); @@ -446,20 +402,20 @@ int feroceon_write_cp15(target_t *target, uint32_t op1, uint32_t op2, uint32_t C return arm7_9_execute_sys_speed(target); } -void feroceon_set_dbgrq(target_t *target) +void feroceon_set_dbgrq(struct target *target) { - armv4_5_common_t *armv4_5 = target->arch_info; - arm7_9_common_t *arm7_9 = armv4_5->arch_info; - reg_t *dbg_ctrl = &arm7_9->eice_cache->reg_list[EICE_DBG_CTRL]; + struct arm *armv4_5 = target->arch_info; + struct arm7_9_common *arm7_9 = armv4_5->arch_info; + struct reg *dbg_ctrl = &arm7_9->eice_cache->reg_list[EICE_DBG_CTRL]; buf_set_u32(dbg_ctrl->value, 0, 8, 2); embeddedice_store_reg(dbg_ctrl); } -void feroceon_enable_single_step(target_t *target, uint32_t next_pc) +void feroceon_enable_single_step(struct target *target, uint32_t next_pc) { - armv4_5_common_t *armv4_5 = target->arch_info; - arm7_9_common_t *arm7_9 = armv4_5->arch_info; + struct arm *armv4_5 = target->arch_info; + struct arm7_9_common *arm7_9 = armv4_5->arch_info; /* set a breakpoint there */ embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_VALUE], next_pc); @@ -469,10 +425,10 @@ void feroceon_enable_single_step(target_t *target, uint32_t next_pc) embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_MASK], 0xf7); } -void feroceon_disable_single_step(target_t *target) +void feroceon_disable_single_step(struct target *target) { - armv4_5_common_t *armv4_5 = target->arch_info; - arm7_9_common_t *arm7_9 = armv4_5->arch_info; + struct arm *armv4_5 = target->arch_info; + struct arm7_9_common *arm7_9 = armv4_5->arch_info; embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_VALUE]); embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_MASK]); @@ -481,7 +437,7 @@ void feroceon_disable_single_step(target_t *target) embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE]); } -int feroceon_examine_debug_reason(target_t *target) +int feroceon_examine_debug_reason(struct target *target) { /* the MOE is not implemented */ if (target->debug_reason != DBG_REASON_SINGLESTEP) @@ -492,11 +448,11 @@ int feroceon_examine_debug_reason(target_t *target) return ERROR_OK; } -int feroceon_bulk_write_memory(target_t *target, uint32_t address, uint32_t count, uint8_t *buffer) +int feroceon_bulk_write_memory(struct target *target, uint32_t address, uint32_t count, uint8_t *buffer) { int retval; - armv4_5_common_t *armv4_5 = target->arch_info; - arm7_9_common_t *arm7_9 = armv4_5->arch_info; + struct arm *armv4_5 = target->arch_info; + struct arm7_9_common *arm7_9 = armv4_5->arch_info; enum armv4_5_state core_state = armv4_5->core_state; uint32_t x, flip, shift, save[7]; uint32_t i; @@ -591,9 +547,20 @@ int feroceon_bulk_write_memory(target_t *target, uint32_t address, uint32_t coun buffer += 4; } - target_halt(target); - while (target->state != TARGET_HALTED) - target_poll(target); + retval = target_halt(target); + if (retval == ERROR_OK) + retval = target_wait_state(target, TARGET_HALTED, 500); + if (retval == ERROR_OK) { + uint32_t endaddress = + buf_get_u32(armv4_5->core_cache->reg_list[0].value, 0, 32); + if (endaddress != address + count*4) { + LOG_ERROR("DCC write failed," + " expected end address 0x%08" PRIx32 + " got 0x%0" PRIx32 "", + address + count*4, endaddress); + retval = ERROR_FAIL; + } + } /* restore target state */ for (i = 0; i <= 5; i++) @@ -607,30 +574,19 @@ int feroceon_bulk_write_memory(target_t *target, uint32_t address, uint32_t coun armv4_5->core_cache->reg_list[15].dirty = 1; armv4_5->core_state = core_state; - return ERROR_OK; + return retval; } -int feroceon_init_target(struct command_context_s *cmd_ctx, struct target_s *target) +int feroceon_init_target(struct command_context *cmd_ctx, struct target *target) { arm9tdmi_init_target(cmd_ctx, target); return ERROR_OK; } -int feroceon_quit(void) +void feroceon_common_setup(struct target *target) { - return ERROR_OK; -} - -int feroceon_target_create(struct target_s *target, Jim_Interp *interp) -{ - armv4_5_common_t *armv4_5; - arm7_9_common_t *arm7_9; - arm926ejs_common_t *arm926ejs = calloc(1,sizeof(arm926ejs_common_t)); - - arm926ejs_init_arch_info(target, arm926ejs, target->tap); - - armv4_5 = target->arch_info; - arm7_9 = armv4_5->arch_info; + struct arm *armv4_5 = target->arch_info; + struct arm7_9_common *arm7_9 = armv4_5->arch_info; /* override some insn sequence functions */ arm7_9->change_to_arm = feroceon_change_to_arm; @@ -650,10 +606,6 @@ int feroceon_target_create(struct target_s *target, Jim_Interp *interp) /* MOE is not implemented */ arm7_9->examine_debug_reason = feroceon_examine_debug_reason; - /* the standard ARM926 methods don't always work (don't ask...) */ - arm926ejs->read_cp15 = feroceon_read_cp15; - arm926ejs->write_cp15 = feroceon_write_cp15; - /* Note: asserting DBGRQ might not win over the undef exception. If that happens then just use "arm7_9 dbgrq disable". */ arm7_9->use_dbgrq = 1; @@ -662,17 +614,39 @@ int feroceon_target_create(struct target_s *target, Jim_Interp *interp) /* only one working comparator */ arm7_9->wp_available_max = 1; arm7_9->wp1_used_default = -1; +} + +int feroceon_target_create(struct target *target, Jim_Interp *interp) +{ + struct arm926ejs_common *arm926ejs = calloc(1,sizeof(struct arm926ejs_common)); + + arm926ejs_init_arch_info(target, arm926ejs, target->tap); + feroceon_common_setup(target); + + /* the standard ARM926 methods don't always work (don't ask...) */ + arm926ejs->read_cp15 = feroceon_read_cp15; + arm926ejs->write_cp15 = feroceon_write_cp15; return ERROR_OK; } -int feroceon_examine(struct target_s *target) +int dragonite_target_create(struct target *target, Jim_Interp *interp) { - armv4_5_common_t *armv4_5; - arm7_9_common_t *arm7_9; + struct arm966e_common *arm966e = calloc(1,sizeof(struct arm966e_common)); + + arm966e_init_arch_info(target, arm966e, target->tap); + feroceon_common_setup(target); + + return ERROR_OK; +} + +int feroceon_examine(struct target *target) +{ + struct arm *armv4_5; + struct arm7_9_common *arm7_9; int retval; - retval = arm9tdmi_examine(target); + retval = arm7_9_examine(target); if (retval != ERROR_OK) return retval; @@ -699,3 +673,82 @@ int feroceon_examine(struct target_s *target) return ERROR_OK; } + +struct target_type feroceon_target = +{ + .name = "feroceon", + + .poll = arm7_9_poll, + .arch_state = arm926ejs_arch_state, + + .target_request_data = arm7_9_target_request_data, + + .halt = arm7_9_halt, + .resume = arm7_9_resume, + .step = arm7_9_step, + + .assert_reset = feroceon_assert_reset, + .deassert_reset = arm7_9_deassert_reset, + .soft_reset_halt = arm926ejs_soft_reset_halt, + + .get_gdb_reg_list = armv4_5_get_gdb_reg_list, + + .read_memory = arm7_9_read_memory, + .write_memory = arm926ejs_write_memory, + .bulk_write_memory = feroceon_bulk_write_memory, + + .checksum_memory = arm_checksum_memory, + .blank_check_memory = arm_blank_check_memory, + + .run_algorithm = armv4_5_run_algorithm, + + .add_breakpoint = arm7_9_add_breakpoint, + .remove_breakpoint = arm7_9_remove_breakpoint, + .add_watchpoint = arm7_9_add_watchpoint, + .remove_watchpoint = arm7_9_remove_watchpoint, + + .register_commands = arm926ejs_register_commands, + .target_create = feroceon_target_create, + .init_target = feroceon_init_target, + .examine = feroceon_examine, +}; + +struct target_type dragonite_target = +{ + .name = "dragonite", + + .poll = arm7_9_poll, + .arch_state = armv4_5_arch_state, + + .target_request_data = arm7_9_target_request_data, + + .halt = arm7_9_halt, + .resume = arm7_9_resume, + .step = arm7_9_step, + + .assert_reset = feroceon_assert_reset, + .deassert_reset = arm7_9_deassert_reset, + .soft_reset_halt = arm7_9_soft_reset_halt, + + .get_gdb_reg_list = armv4_5_get_gdb_reg_list, + + .read_memory = arm7_9_read_memory, + .write_memory = arm7_9_write_memory, + .bulk_write_memory = feroceon_bulk_write_memory, + + .checksum_memory = arm_checksum_memory, + .blank_check_memory = arm_blank_check_memory, + + .run_algorithm = armv4_5_run_algorithm, + + .add_breakpoint = arm7_9_add_breakpoint, + .remove_breakpoint = arm7_9_remove_breakpoint, + .add_watchpoint = arm7_9_add_watchpoint, + .remove_watchpoint = arm7_9_remove_watchpoint, + + .register_commands = arm966e_register_commands, + .target_create = dragonite_target_create, + .init_target = feroceon_init_target, + .examine = feroceon_examine, +}; +