X-Git-Url: https://review.openocd.org/gitweb?a=blobdiff_plain;f=src%2Ftarget%2Fetm.h;h=14dda4fcee895e9722bce0e6cb8cbff8afdc86fe;hb=56a04a3413a6427ef83dc18e3f7c7c13fd217113;hp=da47ff13ab9f67b559b6f9f5ec79ba7d81ab783b;hpb=3d6bcf07921753141a3905ee5619724573460cb3;p=openocd.git

diff --git a/src/target/etm.h b/src/target/etm.h
index da47ff13ab..14dda4fcee 100644
--- a/src/target/etm.h
+++ b/src/target/etm.h
@@ -23,14 +23,12 @@
 #ifndef ETM_H
 #define ETM_H
 
-#include "image.h"
 #include "trace.h"
-#include "target.h"
-#include "register.h"
 #include "arm_jtag.h"
-
 #include "armv4_5.h"
 
+struct image_s;
+
 /* ETM registers (V1.3 protocol) */
 enum
 {
@@ -62,7 +60,7 @@ enum
 	ETM_SEQUENCER_STATE = 0x67,
 	ETM_EXTERNAL_OUTPUT = 0x68,
 	ETM_CONTEXTID_COMPARATOR_VALUE = 0x6c,
-	ETM_CONTEXTID_COMPARATOR_MASK = 0x6f,	
+	ETM_CONTEXTID_COMPARATOR_MASK = 0x6f,
 };
 
 typedef struct etm_reg_s
@@ -77,7 +75,7 @@ typedef enum
 	ETM_PORT_4BIT		= 0x00,
 	ETM_PORT_8BIT		= 0x10,
 	ETM_PORT_16BIT		= 0x20,
-	ETM_PORT_WIDTH_MASK	= 0x70, 
+	ETM_PORT_WIDTH_MASK	= 0x70,
 	/* Port modes */
 	ETM_PORT_NORMAL    = 0x00000,
 	ETM_PORT_MUXED     = 0x10000,
@@ -129,8 +127,8 @@ enum
 
 typedef struct etmv1_trace_data_s
 {
-	u8 pipestat;	/* bits 0-2 pipeline status */
-	u16 packet;		/* packet data (4, 8 or 16 bit) */
+	uint8_t pipestat;	/* bits 0-2 pipeline status */
+	uint16_t packet;		/* packet data (4, 8 or 16 bit) */
 	int flags;		/* ETMV1_TRACESYNC_CYCLE, ETMV1_TRIGGER_CYCLE */
 } etmv1_trace_data_t;
 
@@ -145,25 +143,25 @@ typedef struct etm_context_s
 	reg_cache_t *reg_cache;			/* ETM register cache */
 	etm_capture_driver_t *capture_driver;	/* driver used to access ETM data */
 	void *capture_driver_priv;		/* capture driver private data */
-	u32 trigger_percent;			/* percent of trace buffer to be filled after the trigger */
-	trace_status_t capture_status;	/* current state of capture run */ 
+	uint32_t trigger_percent;			/* percent of trace buffer to be filled after the trigger */
+	trace_status_t capture_status;	/* current state of capture run */
 	etmv1_trace_data_t *trace_data;	/* trace data */
-	u32 trace_depth;				/* number of trace cycles to be analyzed, 0 if no trace data available */
+	uint32_t trace_depth;				/* number of trace cycles to be analyzed, 0 if no trace data available */
 	etm_portmode_t portmode;		/* normal, multiplexed or demultiplexed */
-	etmv1_tracemode_t tracemode;	/* type of information the trace contains (data, addres, contextID, ...) */ 
+	etmv1_tracemode_t tracemode;	/* type of information the trace contains (data, addres, contextID, ...) */
 	armv4_5_state_t core_state;		/* current core state (ARM, Thumb, Jazelle) */
-	image_t *image;					/* source for target opcodes */
-	u32 pipe_index;					/* current trace cycle */
-	u32 data_index;					/* cycle holding next data packet */
+	struct image_s *image;					/* source for target opcodes */
+	uint32_t pipe_index;					/* current trace cycle */
+	uint32_t data_index;					/* cycle holding next data packet */
 	int data_half;					/* port half on a 16 bit port */
-	u32 current_pc;					/* current program counter */
-	u32 pc_ok;						/* full PC has been acquired */
-	u32 last_branch;				/* last branch address output */ 
-	u32 last_branch_reason;			/* branch reason code for the last branch encountered */
-	u32 last_ptr;					/* address of the last data access */
-	u32 ptr_ok;						/* whether last_ptr is valid */ 
-	u32 context_id;					/* context ID of the code being traced */
-	u32 last_instruction;			/* index of last instruction executed (to calculate cycle timings) */
+	uint32_t current_pc;					/* current program counter */
+	uint32_t pc_ok;						/* full PC has been acquired */
+	uint32_t last_branch;				/* last branch address output */
+	uint32_t last_branch_reason;			/* branch reason code for the last branch encountered */
+	uint32_t last_ptr;					/* address of the last data access */
+	uint32_t ptr_ok;						/* whether last_ptr is valid */
+	uint32_t context_id;					/* context ID of the code being traced */
+	uint32_t last_instruction;			/* index of last instruction executed (to calculate cycle timings) */
 } etm_context_t;
 
 /* PIPESTAT values */
@@ -186,7 +184,7 @@ typedef enum
 	BR_ENABLE  = 0x1, /* Trace has been enabled */
 	BR_RESTART = 0x2, /* Trace restarted after a FIFO overflow */
 	BR_NODEBUG = 0x3, /* ARM has exited for debug state */
-	BR_PERIOD  = 0x4, /* Peridioc synchronization point (ETM>=v1.2)*/
+	BR_PERIOD  = 0x4, /* Peridioc synchronization point (ETM >= v1.2)*/
 	BR_RSVD5   = 0x5, /* reserved */
 	BR_RSVD6   = 0x6, /* reserved */
 	BR_RSVD7   = 0x7, /* reserved */
@@ -196,11 +194,12 @@ extern char *etmv1v1_branch_reason_strings[];
 
 extern reg_cache_t* etm_build_reg_cache(target_t *target, arm_jtag_t *jtag_info, etm_context_t *etm_ctx);
 extern int etm_read_reg(reg_t *reg);
-extern int etm_write_reg(reg_t *reg, u32 value);
-extern int etm_read_reg_w_check(reg_t *reg, u8* check_value, u8* check_mask);
+extern int etm_write_reg(reg_t *reg, uint32_t value);
+extern int etm_read_reg_w_check(reg_t *reg, uint8_t* check_value, uint8_t* check_mask);
 extern int etm_store_reg(reg_t *reg);
-extern int etm_set_reg(reg_t *reg, u32 value);
-extern int etm_set_reg_w_exec(reg_t *reg, u8 *buf);
+extern int etm_set_reg(reg_t *reg, uint32_t value);
+extern int etm_set_reg_w_exec(reg_t *reg, uint8_t *buf);
+extern int etm_setup(target_t *target);
 
 int etm_register_commands(struct command_context_s *cmd_ctx);
 int etm_register_user_commands(struct command_context_s *cmd_ctx);