X-Git-Url: https://review.openocd.org/gitweb?a=blobdiff_plain;f=src%2Ftarget%2Fetb.c;h=a327fb6bd48a1f841780ec61937fd642eb873dcd;hb=dc575dc5bf8cb597a0e9a47794744ae6b1928087;hp=cfaf1cdcd88d66b67601beb778e8daecf271c8ca;hpb=c45de8073d027f1a4d39640dc140666f27960e3b;p=openocd.git

diff --git a/src/target/etb.c b/src/target/etb.c
index cfaf1cdcd8..a327fb6bd4 100644
--- a/src/target/etb.c
+++ b/src/target/etb.c
@@ -21,22 +21,11 @@
 #include "config.h"
 #endif
 
-#include <string.h>
-
 #include "arm7_9_common.h"
 #include "etb.h"
-#include "etm.h"
-
-#include "log.h"
-#include "types.h"
-#include "binarybuffer.h"
-#include "target.h"
-#include "register.h"
-#include "jtag.h"
 
-#include <stdlib.h>
 
-char* etb_reg_list[] =
+static char* etb_reg_list[] =
 {
 	"ETB_identification",
 	"ETB_ram_depth",
@@ -49,22 +38,18 @@ char* etb_reg_list[] =
 	"ETB_control",
 };
 
-int etb_reg_arch_type = -1;
-
-int etb_get_reg(reg_t *reg);
-int etb_set_reg(reg_t *reg, u32 value);
-int etb_set_reg_w_exec(reg_t *reg, u8 *buf);
+static int etb_reg_arch_type = -1;
 
-int etb_write_reg(reg_t *reg, u32 value);
-int etb_read_reg(reg_t *reg);
+static int etb_get_reg(reg_t *reg);
 
-int handle_etb_config_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
+static int handle_etb_config_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
 
-int etb_set_instr(etb_t *etb, u32 new_instr)
+static int etb_set_instr(etb_t *etb, uint32_t new_instr)
 {
 	jtag_tap_t *tap;
+
 	tap = etb->tap;
-	if (tap==NULL)
+	if (tap == NULL)
 		return ERROR_FAIL;
 
 	if (buf_get_u32(tap->cur_instr, 0, tap->ir_length) != new_instr)
@@ -75,14 +60,10 @@ int etb_set_instr(etb_t *etb, u32 new_instr)
 		field.num_bits = tap->ir_length;
 		field.out_value = calloc(CEIL(field.num_bits, 8), 1);
 		buf_set_u32(field.out_value, 0, field.num_bits, new_instr);
-		field.out_mask = NULL;
+
 		field.in_value = NULL;
-		field.in_check_value = NULL;
-		field.in_check_mask = NULL;
-		field.in_handler = NULL;
-		field.in_handler_priv = NULL;
 
-		jtag_add_ir_scan(1, &field, -1);
+		jtag_add_ir_scan(1, &field, jtag_get_end_state());
 
 		free(field.out_value);
 	}
@@ -90,9 +71,9 @@ int etb_set_instr(etb_t *etb, u32 new_instr)
 	return ERROR_OK;
 }
 
-int etb_scann(etb_t *etb, u32 new_scan_chain)
+static int etb_scann(etb_t *etb, uint32_t new_scan_chain)
 {
-	if(etb->cur_scan_chain != new_scan_chain)
+	if (etb->cur_scan_chain != new_scan_chain)
 	{
 		scan_field_t field;
 
@@ -100,16 +81,12 @@ int etb_scann(etb_t *etb, u32 new_scan_chain)
 		field.num_bits = 5;
 		field.out_value = calloc(CEIL(field.num_bits, 8), 1);
 		buf_set_u32(field.out_value, 0, field.num_bits, new_scan_chain);
-		field.out_mask = NULL;
+
 		field.in_value = NULL;
-		field.in_check_value = NULL;
-		field.in_check_mask = NULL;
-		field.in_handler = NULL;
-		field.in_handler_priv = NULL;
 
 		/* select INTEST instruction */
 		etb_set_instr(etb, 0x2);
-		jtag_add_dr_scan(1, &field, -1);
+		jtag_add_dr_scan(1, &field, jtag_get_end_state());
 
 		etb->cur_scan_chain = new_scan_chain;
 
@@ -161,9 +138,10 @@ reg_cache_t* etb_build_reg_cache(etb_t *etb)
 	return reg_cache;
 }
 
-int etb_get_reg(reg_t *reg)
+static int etb_get_reg(reg_t *reg)
 {
 	int retval;
+
 	if ((retval = etb_read_reg(reg)) != ERROR_OK)
 	{
 		LOG_ERROR("BUG: error scheduling etm register read");
@@ -179,50 +157,41 @@ int etb_get_reg(reg_t *reg)
 	return ERROR_OK;
 }
 
-int etb_read_ram(etb_t *etb, u32 *data, int num_frames)
+
+static void etb_getbuf(jtag_callback_data_t arg)
+{
+  uint8_t *in = (uint8_t *)arg;
+	*((uint32_t *)in) = buf_get_u32(in, 0, 32);
+}
+
+
+static int etb_read_ram(etb_t *etb, uint32_t *data, int num_frames)
 {
 	scan_field_t fields[3];
 	int i;
 
-	jtag_add_end_state(TAP_IDLE);
+	jtag_set_end_state(TAP_IDLE);
 	etb_scann(etb, 0x0);
 	etb_set_instr(etb, 0xc);
 
 	fields[0].tap = etb->tap;
 	fields[0].num_bits = 32;
 	fields[0].out_value = NULL;
-	fields[0].out_mask = NULL;
 	fields[0].in_value = NULL;
-	fields[0].in_check_value = NULL;
-	fields[0].in_check_mask = NULL;
-	fields[0].in_handler = NULL;
-	fields[0].in_handler_priv = NULL;
 
 	fields[1].tap = etb->tap;
 	fields[1].num_bits = 7;
 	fields[1].out_value = malloc(1);
 	buf_set_u32(fields[1].out_value, 0, 7, 4);
-	fields[1].out_mask = NULL;
 	fields[1].in_value = NULL;
-	fields[1].in_check_value = NULL;
-	fields[1].in_check_mask = NULL;
-	fields[1].in_handler = NULL;
-	fields[1].in_handler_priv = NULL;
 
 	fields[2].tap = etb->tap;
 	fields[2].num_bits = 1;
 	fields[2].out_value = malloc(1);
 	buf_set_u32(fields[2].out_value, 0, 1, 0);
-	fields[2].out_mask = NULL;
 	fields[2].in_value = NULL;
-	fields[2].in_check_value = NULL;
-	fields[2].in_check_mask = NULL;
-	fields[2].in_handler = NULL;
-	fields[2].in_handler_priv = NULL;
-
-	jtag_add_dr_scan(3, fields, -1);
 
-	fields[0].in_handler = buf_to_u32_handler;
+	jtag_add_dr_scan(3, fields, jtag_get_end_state());
 
 	for (i = 0; i < num_frames; i++)
 	{
@@ -235,8 +204,10 @@ int etb_read_ram(etb_t *etb, u32 *data, int num_frames)
 		else
 			buf_set_u32(fields[1].out_value, 0, 7, 0);
 
-		fields[0].in_handler_priv = &data[i];
-		jtag_add_dr_scan(3, fields, -1);
+		fields[0].in_value = (uint8_t *)(data + i);
+		jtag_add_dr_scan(3, fields, jtag_get_end_state());
+
+		jtag_add_callback(etb_getbuf, (jtag_callback_data_t)(data + i));
 	}
 
 	jtag_execute_queue();
@@ -247,61 +218,52 @@ int etb_read_ram(etb_t *etb, u32 *data, int num_frames)
 	return ERROR_OK;
 }
 
-int etb_read_reg_w_check(reg_t *reg, u8* check_value, u8* check_mask)
+int etb_read_reg_w_check(reg_t *reg, uint8_t* check_value, uint8_t* check_mask)
 {
 	etb_reg_t *etb_reg = reg->arch_info;
-	u8 reg_addr = etb_reg->addr & 0x7f;
+	uint8_t reg_addr = etb_reg->addr & 0x7f;
 	scan_field_t fields[3];
 
-	LOG_DEBUG("%i", etb_reg->addr);
+	LOG_DEBUG("%i", (int)(etb_reg->addr));
 
-	jtag_add_end_state(TAP_IDLE);
+	jtag_set_end_state(TAP_IDLE);
 	etb_scann(etb_reg->etb, 0x0);
 	etb_set_instr(etb_reg->etb, 0xc);
 
 	fields[0].tap = etb_reg->etb->tap;
 	fields[0].num_bits = 32;
 	fields[0].out_value = reg->value;
-	fields[0].out_mask = NULL;
 	fields[0].in_value = NULL;
-	fields[0].in_check_value = NULL;
-	fields[0].in_check_mask = NULL;
-	fields[0].in_handler = NULL;
-	fields[0].in_handler_priv = NULL;
+	fields[0].check_value = NULL;
+	fields[0].check_mask = NULL;
 
 	fields[1].tap = etb_reg->etb->tap;
 	fields[1].num_bits = 7;
 	fields[1].out_value = malloc(1);
 	buf_set_u32(fields[1].out_value, 0, 7, reg_addr);
-	fields[1].out_mask = NULL;
 	fields[1].in_value = NULL;
-	fields[1].in_check_value = NULL;
-	fields[1].in_check_mask = NULL;
-	fields[1].in_handler = NULL;
-	fields[1].in_handler_priv = NULL;
+	fields[1].check_value = NULL;
+	fields[1].check_mask = NULL;
 
 	fields[2].tap = etb_reg->etb->tap;
 	fields[2].num_bits = 1;
 	fields[2].out_value = malloc(1);
 	buf_set_u32(fields[2].out_value, 0, 1, 0);
-	fields[2].out_mask = NULL;
 	fields[2].in_value = NULL;
-	fields[2].in_check_value = NULL;
-	fields[2].in_check_mask = NULL;
-	fields[2].in_handler = NULL;
-	fields[2].in_handler_priv = NULL;
+	fields[2].check_value = NULL;
+	fields[2].check_mask = NULL;
 
-	jtag_add_dr_scan(3, fields, -1);
+	jtag_add_dr_scan(3, fields, jtag_get_end_state());
 
 	/* read the identification register in the second run, to make sure we
 	 * don't read the ETB data register twice, skipping every second entry
 	 */
 	buf_set_u32(fields[1].out_value, 0, 7, 0x0);
 	fields[0].in_value = reg->value;
+	fields[0].check_value = check_value;
+	fields[0].check_mask = check_mask;
 
-	jtag_set_check_value(fields+0, check_value, check_mask, NULL);
-
-	jtag_add_dr_scan(3, fields, -1);
+	jtag_add_dr_scan_check(3, fields, jtag_get_end_state());
 
 	free(fields[1].out_value);
 	free(fields[2].out_value);
@@ -314,9 +276,10 @@ int etb_read_reg(reg_t *reg)
 	return etb_read_reg_w_check(reg, NULL, NULL);
 }
 
-int etb_set_reg(reg_t *reg, u32 value)
+int etb_set_reg(reg_t *reg, uint32_t value)
 {
 	int retval;
+
 	if ((retval = etb_write_reg(reg, value)) != ERROR_OK)
 	{
 		LOG_ERROR("BUG: error scheduling etm register write");
@@ -330,9 +293,10 @@ int etb_set_reg(reg_t *reg, u32 value)
 	return ERROR_OK;
 }
 
-int etb_set_reg_w_exec(reg_t *reg, u8 *buf)
+int etb_set_reg_w_exec(reg_t *reg, uint8_t *buf)
 {
 	int retval;
+
 	etb_set_reg(reg, buf_get_u32(buf, 0, reg->size));
 
 	if ((retval = jtag_execute_queue()) != ERROR_OK)
@@ -343,15 +307,15 @@ int etb_set_reg_w_exec(reg_t *reg, u8 *buf)
 	return ERROR_OK;
 }
 
-int etb_write_reg(reg_t *reg, u32 value)
+int etb_write_reg(reg_t *reg, uint32_t value)
 {
 	etb_reg_t *etb_reg = reg->arch_info;
-	u8 reg_addr = etb_reg->addr & 0x7f;
+	uint8_t reg_addr = etb_reg->addr & 0x7f;
 	scan_field_t fields[3];
 
-	LOG_DEBUG("%i: 0x%8.8x", etb_reg->addr, value);
+	LOG_DEBUG("%i: 0x%8.8" PRIx32 "", (int)(etb_reg->addr), value);
 
-	jtag_add_end_state(TAP_IDLE);
+	jtag_set_end_state(TAP_IDLE);
 	etb_scann(etb_reg->etb, 0x0);
 	etb_set_instr(etb_reg->etb, 0xc);
 
@@ -359,36 +323,20 @@ int etb_write_reg(reg_t *reg, u32 value)
 	fields[0].num_bits = 32;
 	fields[0].out_value = malloc(4);
 	buf_set_u32(fields[0].out_value, 0, 32, value);
-	fields[0].out_mask = NULL;
 	fields[0].in_value = NULL;
-	fields[0].in_check_value = NULL;
-	fields[0].in_check_mask = NULL;
-	fields[0].in_handler = NULL;
-	fields[0].in_handler_priv = NULL;
 
 	fields[1].tap = etb_reg->etb->tap;
 	fields[1].num_bits = 7;
 	fields[1].out_value = malloc(1);
 	buf_set_u32(fields[1].out_value, 0, 7, reg_addr);
-	fields[1].out_mask = NULL;
 	fields[1].in_value = NULL;
-	fields[1].in_check_value = NULL;
-	fields[1].in_check_mask = NULL;
-	fields[1].in_handler = NULL;
-	fields[1].in_handler_priv = NULL;
 
 	fields[2].tap = etb_reg->etb->tap;
 	fields[2].num_bits = 1;
 	fields[2].out_value = malloc(1);
 	buf_set_u32(fields[2].out_value, 0, 1, 1);
-	fields[2].out_mask = NULL;
-	fields[2].in_value = NULL;
-	fields[2].in_check_value = NULL;
-	fields[2].in_check_mask = NULL;
-	fields[2].in_handler = NULL;
-	fields[2].in_handler_priv = NULL;
 
-	jtag_add_dr_scan(3, fields, -1);
+	fields[2].in_value = NULL;
 
 	free(fields[0].out_value);
 	free(fields[1].out_value);
@@ -402,7 +350,7 @@ int etb_store_reg(reg_t *reg)
 	return etb_write_reg(reg, buf_get_u32(reg->value, 0, reg->size));
 }
 
-int etb_register_commands(struct command_context_s *cmd_ctx)
+static int etb_register_commands(struct command_context_s *cmd_ctx)
 {
 	command_t *etb_cmd;
 
@@ -413,7 +361,7 @@ int etb_register_commands(struct command_context_s *cmd_ctx)
 	return ERROR_OK;
 }
 
-int handle_etb_config_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
+static int handle_etb_config_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
 {
 	target_t *target;
 	jtag_tap_t *tap;
@@ -425,11 +373,11 @@ int handle_etb_config_command(struct command_context_s *cmd_ctx, char *cmd, char
 		return ERROR_COMMAND_SYNTAX_ERROR;
 	}
 
-	target = get_target_by_num(strtoul(args[0], NULL, 0));
+	target = get_target(args[0]);
 
 	if (!target)
 	{
-		LOG_ERROR("target number '%s' not defined", args[0]);
+		LOG_ERROR("target '%s' not defined", args[0]);
 		return ERROR_FAIL;
 	}
 
@@ -439,13 +387,13 @@ int handle_etb_config_command(struct command_context_s *cmd_ctx, char *cmd, char
 		return ERROR_FAIL;
 	}
 
-	tap = jtag_TapByString( args[1] );
-	if( tap == NULL ){
-		command_print(cmd_ctx, "Tap: %s does not exist", args[1] );
+	tap = jtag_tap_by_string(args[1]);
+	if (tap == NULL)
+	{
+		command_print(cmd_ctx, "Tap: %s does not exist", args[1]);
 		return ERROR_FAIL;
 	}
 
-
 	if (arm7_9->etm_ctx)
 	{
 		etb_t *etb = malloc(sizeof(etb_t));
@@ -453,7 +401,7 @@ int handle_etb_config_command(struct command_context_s *cmd_ctx, char *cmd, char
 		arm7_9->etm_ctx->capture_driver_priv = etb;
 
 		etb->tap  = tap;
-		etb->cur_scan_chain = -1;
+		etb->cur_scan_chain = 0xffffffff;
 		etb->reg_cache = NULL;
 		etb->ram_width = 0;
 		etb->ram_depth = 0;
@@ -467,7 +415,7 @@ int handle_etb_config_command(struct command_context_s *cmd_ctx, char *cmd, char
 	return ERROR_OK;
 }
 
-int etb_init(etm_context_t *etm_ctx)
+static int etb_init(etm_context_t *etm_ctx)
 {
 	etb_t *etb = etm_ctx->capture_driver_priv;
 
@@ -484,7 +432,7 @@ int etb_init(etm_context_t *etm_ctx)
 	return ERROR_OK;
 }
 
-trace_status_t etb_status(etm_context_t *etm_ctx)
+static trace_status_t etb_status(etm_context_t *etm_ctx)
 {
 	etb_t *etb = etm_ctx->capture_driver_priv;
 
@@ -522,7 +470,7 @@ trace_status_t etb_status(etm_context_t *etm_ctx)
 
 			if (etb_timeout == 0)
 			{
-				LOG_ERROR("AcqComp set but DFEmpty won't go high, ETB status: 0x%x",
+				LOG_ERROR("AcqComp set but DFEmpty won't go high, ETB status: 0x%" PRIx32 "",
 					buf_get_u32(etb_status_reg->value, 0, etb_status_reg->size));
 			}
 
@@ -539,12 +487,12 @@ trace_status_t etb_status(etm_context_t *etm_ctx)
 	return etm_ctx->capture_status;
 }
 
-int etb_read_trace(etm_context_t *etm_ctx)
+static int etb_read_trace(etm_context_t *etm_ctx)
 {
 	etb_t *etb = etm_ctx->capture_driver_priv;
 	int first_frame = 0;
 	int num_frames = etb->ram_depth;
-	u32 *trace_data = NULL;
+	uint32_t *trace_data = NULL;
 	int i, j;
 
 	etb_read_reg(&etb->reg_cache->reg_list[ETB_STATUS]);
@@ -567,7 +515,7 @@ int etb_read_trace(etm_context_t *etm_ctx)
 	etb_write_reg(&etb->reg_cache->reg_list[ETB_RAM_READ_POINTER], first_frame);
 
 	/* read data into temporary array for unpacking */
-	trace_data = malloc(sizeof(u32) * num_frames);
+	trace_data = malloc(sizeof(uint32_t) * num_frames);
 	etb_read_ram(etb, trace_data, num_frames);
 
 	if (etm_ctx->trace_depth > 0)
@@ -602,32 +550,32 @@ int etb_read_trace(etm_context_t *etm_ctx)
 				etm_ctx->trace_data[j].flags |= ETMV1_TRIGGER_CYCLE;
 			}
 
-			/* trace word j+1 */
-			etm_ctx->trace_data[j+1].pipestat = (trace_data[i] & 0x100) >> 8;
-			etm_ctx->trace_data[j+1].packet = (trace_data[i] & 0x7800) >> 11;
-			etm_ctx->trace_data[j+1].flags = 0;
+			/* trace word j + 1 */
+			etm_ctx->trace_data[j + 1].pipestat = (trace_data[i] & 0x100) >> 8;
+			etm_ctx->trace_data[j + 1].packet = (trace_data[i] & 0x7800) >> 11;
+			etm_ctx->trace_data[j + 1].flags = 0;
 			if ((trace_data[i] & 0x8000) >> 15)
 			{
-				etm_ctx->trace_data[j+1].flags |= ETMV1_TRACESYNC_CYCLE;
+				etm_ctx->trace_data[j + 1].flags |= ETMV1_TRACESYNC_CYCLE;
 			}
-			if (etm_ctx->trace_data[j+1].pipestat == STAT_TR)
+			if (etm_ctx->trace_data[j + 1].pipestat == STAT_TR)
 			{
-				etm_ctx->trace_data[j+1].pipestat = etm_ctx->trace_data[j+1].packet & 0x7;
-				etm_ctx->trace_data[j+1].flags |= ETMV1_TRIGGER_CYCLE;
+				etm_ctx->trace_data[j + 1].pipestat = etm_ctx->trace_data[j + 1].packet & 0x7;
+				etm_ctx->trace_data[j + 1].flags |= ETMV1_TRIGGER_CYCLE;
 			}
 
-			/* trace word j+2 */
-			etm_ctx->trace_data[j+2].pipestat = (trace_data[i] & 0x10000) >> 16;
-			etm_ctx->trace_data[j+2].packet = (trace_data[i] & 0x780000) >> 19;
-			etm_ctx->trace_data[j+2].flags = 0;
+			/* trace word j + 2 */
+			etm_ctx->trace_data[j + 2].pipestat = (trace_data[i] & 0x10000) >> 16;
+			etm_ctx->trace_data[j + 2].packet = (trace_data[i] & 0x780000) >> 19;
+			etm_ctx->trace_data[j + 2].flags = 0;
 			if ((trace_data[i] & 0x800000) >> 23)
 			{
-				etm_ctx->trace_data[j+2].flags |= ETMV1_TRACESYNC_CYCLE;
+				etm_ctx->trace_data[j + 2].flags |= ETMV1_TRACESYNC_CYCLE;
 			}
-			if (etm_ctx->trace_data[j+2].pipestat == STAT_TR)
+			if (etm_ctx->trace_data[j + 2].pipestat == STAT_TR)
 			{
-				etm_ctx->trace_data[j+2].pipestat = etm_ctx->trace_data[j+2].packet & 0x7;
-				etm_ctx->trace_data[j+2].flags |= ETMV1_TRIGGER_CYCLE;
+				etm_ctx->trace_data[j + 2].pipestat = etm_ctx->trace_data[j + 2].packet & 0x7;
+				etm_ctx->trace_data[j + 2].flags |= ETMV1_TRIGGER_CYCLE;
 			}
 
 			j += 3;
@@ -648,18 +596,18 @@ int etb_read_trace(etm_context_t *etm_ctx)
 				etm_ctx->trace_data[j].flags |= ETMV1_TRIGGER_CYCLE;
 			}
 
-			/* trace word j+1 */
-			etm_ctx->trace_data[j+1].pipestat = (trace_data[i] & 0x7000) >> 12;
-			etm_ctx->trace_data[j+1].packet = (trace_data[i] & 0x7f8000) >> 15;
-			etm_ctx->trace_data[j+1].flags = 0;
+			/* trace word j + 1 */
+			etm_ctx->trace_data[j + 1].pipestat = (trace_data[i] & 0x7000) >> 12;
+			etm_ctx->trace_data[j + 1].packet = (trace_data[i] & 0x7f8000) >> 15;
+			etm_ctx->trace_data[j + 1].flags = 0;
 			if ((trace_data[i] & 0x800000) >> 23)
 			{
-				etm_ctx->trace_data[j+1].flags |= ETMV1_TRACESYNC_CYCLE;
+				etm_ctx->trace_data[j + 1].flags |= ETMV1_TRACESYNC_CYCLE;
 			}
-			if (etm_ctx->trace_data[j+1].pipestat == STAT_TR)
+			if (etm_ctx->trace_data[j + 1].pipestat == STAT_TR)
 			{
-				etm_ctx->trace_data[j+1].pipestat = etm_ctx->trace_data[j+1].packet & 0x7;
-				etm_ctx->trace_data[j+1].flags |= ETMV1_TRIGGER_CYCLE;
+				etm_ctx->trace_data[j + 1].pipestat = etm_ctx->trace_data[j + 1].packet & 0x7;
+				etm_ctx->trace_data[j + 1].flags |= ETMV1_TRIGGER_CYCLE;
 			}
 
 			j += 2;
@@ -689,11 +637,11 @@ int etb_read_trace(etm_context_t *etm_ctx)
 	return ERROR_OK;
 }
 
-int etb_start_capture(etm_context_t *etm_ctx)
+static int etb_start_capture(etm_context_t *etm_ctx)
 {
 	etb_t *etb = etm_ctx->capture_driver_priv;
-	u32 etb_ctrl_value = 0x1;
-	u32 trigger_count;
+	uint32_t etb_ctrl_value = 0x1;
+	uint32_t trigger_count;
 
 	if ((etm_ctx->portmode & ETM_PORT_MODE_MASK) == ETM_PORT_DEMUXED)
 	{
@@ -721,7 +669,7 @@ int etb_start_capture(etm_context_t *etm_ctx)
 	return ERROR_OK;
 }
 
-int etb_stop_capture(etm_context_t *etm_ctx)
+static int etb_stop_capture(etm_context_t *etm_ctx)
 {
 	etb_t *etb = etm_ctx->capture_driver_priv;
 	reg_t *etb_ctrl_reg = &etb->reg_cache->reg_list[ETB_CTRL];