X-Git-Url: https://review.openocd.org/gitweb?a=blobdiff_plain;f=src%2Ftarget%2Fembeddedice.c;h=bf220364e653a33630a426e243b8faefeb8747f6;hb=465a06dfdc6c5d4af377dac7b9d71845cb0dc034;hp=a1eac134140792f07b34ebf904c3d0cac5444d8b;hpb=d0809ac060b35a04e7f0bceb96e1868663bd18df;p=openocd.git diff --git a/src/target/embeddedice.c b/src/target/embeddedice.c index a1eac13414..bf220364e6 100644 --- a/src/target/embeddedice.c +++ b/src/target/embeddedice.c @@ -28,15 +28,15 @@ #endif #include "embeddedice.h" - -#define ARRAY_SIZE(x) ((int)(sizeof(x)/sizeof((x)[0]))) +#include "register.h" /** * @file * * This provides lowlevel glue to the EmbeddedICE (or EmbeddedICE-RT) * module found on scan chain 2 in ARM7, ARM9, and some other families - * of ARM cores. + * of ARM cores. The module is called "EmbeddedICE-RT" if it has + * monitor mode support. * * EmbeddedICE provides basic watchpoint/breakpoint hardware and a Debug * Communications Channel (DCC) used to read or write 32-bit words to @@ -144,9 +144,7 @@ static const struct { }; -static int embeddedice_reg_arch_type = -1; - -static int embeddedice_get_reg(reg_t *reg) +static int embeddedice_get_reg(struct reg *reg) { int retval; @@ -158,35 +156,35 @@ static int embeddedice_get_reg(reg_t *reg) return retval; } +static const struct reg_arch_type eice_reg_type = { + .get = embeddedice_get_reg, + .set = embeddedice_set_reg_w_exec, +}; + /** * Probe EmbeddedICE module and set up local records of its registers. * Different versions of the modules have different capabilities, such as * hardware support for vector_catch, single stepping, and monitor mode. */ -reg_cache_t * -embeddedice_build_reg_cache(target_t *target, arm7_9_common_t *arm7_9) +struct reg_cache * +embeddedice_build_reg_cache(struct target *target, struct arm7_9_common *arm7_9) { int retval; - reg_cache_t *reg_cache = malloc(sizeof(reg_cache_t)); - reg_t *reg_list = NULL; - embeddedice_reg_t *arch_info = NULL; - arm_jtag_t *jtag_info = &arm7_9->jtag_info; + struct reg_cache *reg_cache = malloc(sizeof(struct reg_cache)); + struct reg *reg_list = NULL; + struct embeddedice_reg *arch_info = NULL; + struct arm_jtag *jtag_info = &arm7_9->jtag_info; int num_regs = ARRAY_SIZE(eice_regs); int i; int eice_version = 0; - /* register arch-type for EmbeddedICE registers only once */ - if (embeddedice_reg_arch_type == -1) - embeddedice_reg_arch_type = register_reg_arch_type( - embeddedice_get_reg, embeddedice_set_reg_w_exec); - /* vector_catch isn't always present */ if (!arm7_9->has_vector_catch) num_regs--; /* the actual registers are kept in two arrays */ - reg_list = calloc(num_regs, sizeof(reg_t)); - arch_info = calloc(num_regs, sizeof(embeddedice_reg_t)); + reg_list = calloc(num_regs, sizeof(struct reg)); + arch_info = calloc(num_regs, sizeof(struct embeddedice_reg)); /* fill in values for the reg cache */ reg_cache->name = "EmbeddedICE registers"; @@ -194,6 +192,11 @@ embeddedice_build_reg_cache(target_t *target, arm7_9_common_t *arm7_9) reg_cache->reg_list = reg_list; reg_cache->num_regs = num_regs; + /* FIXME the second watchpoint unit on Feroceon and Dragonite + * seems not to work ... we should have a way to not set up + * its four registers here! + */ + /* set up registers */ for (i = 0; i < num_regs; i++) { @@ -201,11 +204,9 @@ embeddedice_build_reg_cache(target_t *target, arm7_9_common_t *arm7_9) reg_list[i].size = eice_regs[i].width; reg_list[i].dirty = 0; reg_list[i].valid = 0; - reg_list[i].bitfield_desc = NULL; - reg_list[i].num_bitfields = 0; reg_list[i].value = calloc(1, 4); reg_list[i].arch_info = &arch_info[i]; - reg_list[i].arch_type = embeddedice_reg_arch_type; + reg_list[i].type = &eice_reg_type; arch_info[i].addr = eice_regs[i].addr; arch_info[i].jtag_info = jtag_info; } @@ -286,24 +287,29 @@ embeddedice_build_reg_cache(target_t *target, arm7_9_common_t *arm7_9) * in some unusual bits. Let feroceon.c validate it * and do the appropriate setup itself. */ - if (strcmp(target_get_name(target), "feroceon") == 0 || - strcmp(target_get_name(target), "dragonite") == 0) + if (strcmp(target_type_name(target), "feroceon") == 0 || + strcmp(target_type_name(target), "dragonite") == 0) break; LOG_ERROR("unknown EmbeddedICE version " "(comms ctrl: 0x%8.8" PRIx32 ")", buf_get_u32(reg_list[EICE_COMMS_CTRL].value, 0, 32)); } + /* On Feroceon and Dragonite the second unit is seemingly missing. */ + LOG_INFO("%s: hardware has %d breakpoint/watchpoint unit%s", + target_name(target), arm7_9->wp_available_max, + (arm7_9->wp_available_max != 1) ? "s" : ""); + return reg_cache; } /** * Initialize EmbeddedICE module, if needed. */ -int embeddedice_setup(target_t *target) +int embeddedice_setup(struct target *target) { int retval; - struct arm7_9_common_s *arm7_9 = target_to_arm7_9(target); + struct arm7_9_common *arm7_9 = target_to_arm7_9(target); /* Explicitly disable monitor mode. For now we only support halting * debug ... we don't know how to talk with a resident debug monitor @@ -312,7 +318,7 @@ int embeddedice_setup(target_t *target) */ if (arm7_9->has_monitor_mode) { - reg_t *dbg_ctrl = &arm7_9->eice_cache->reg_list[EICE_DBG_CTRL]; + struct reg *dbg_ctrl = &arm7_9->eice_cache->reg_list[EICE_DBG_CTRL]; embeddedice_read_reg(dbg_ctrl); if ((retval = jtag_execute_queue()) != ERROR_OK) @@ -328,10 +334,10 @@ int embeddedice_setup(target_t *target) * optionally checking the value read. * Note that at this level, all registers are 32 bits wide. */ -int embeddedice_read_reg_w_check(reg_t *reg, +int embeddedice_read_reg_w_check(struct reg *reg, uint8_t *check_value, uint8_t *check_mask) { - embeddedice_reg_t *ice_reg = reg->arch_info; + struct embeddedice_reg *ice_reg = reg->arch_info; uint8_t reg_addr = ice_reg->addr & 0x1f; struct scan_field fields[3]; uint8_t field1_out[1]; @@ -354,7 +360,7 @@ int embeddedice_read_reg_w_check(reg_t *reg, fields[1].tap = ice_reg->jtag_info->tap; fields[1].num_bits = 5; fields[1].out_value = field1_out; - buf_set_u32(fields[1].out_value, 0, 5, reg_addr); + fields[1].out_value[0] = reg_addr; fields[1].in_value = NULL; fields[1].check_value = NULL; fields[1].check_mask = NULL; @@ -363,7 +369,7 @@ int embeddedice_read_reg_w_check(reg_t *reg, fields[2].tap = ice_reg->jtag_info->tap; fields[2].num_bits = 1; fields[2].out_value = field2_out; - buf_set_u32(fields[2].out_value, 0, 1, 0); + fields[2].out_value[0] = 0; fields[2].in_value = NULL; fields[2].check_value = NULL; fields[2].check_mask = NULL; @@ -380,7 +386,7 @@ int embeddedice_read_reg_w_check(reg_t *reg, * EICE_COMMS_DATA would read the register twice * reading the control register is safe */ - buf_set_u32(fields[1].out_value, 0, 5, eice_regs[EICE_COMMS_CTRL].addr); + fields[1].out_value[0] = eice_regs[EICE_COMMS_CTRL].addr; /* traverse Update-DR, reading but with no other side effects */ jtag_add_dr_scan_check(3, fields, jtag_get_end_state()); @@ -396,7 +402,7 @@ int embeddedice_read_reg_w_check(reg_t *reg, * functional clock, so the 50+ JTAG clocks needed to receive the word * allow hundreds of instruction cycles (per word) in the target. */ -int embeddedice_receive(arm_jtag_t *jtag_info, uint32_t *data, uint32_t size) +int embeddedice_receive(struct arm_jtag *jtag_info, uint32_t *data, uint32_t size) { struct scan_field fields[3]; uint8_t field1_out[1]; @@ -414,13 +420,13 @@ int embeddedice_receive(arm_jtag_t *jtag_info, uint32_t *data, uint32_t size) fields[1].tap = jtag_info->tap; fields[1].num_bits = 5; fields[1].out_value = field1_out; - buf_set_u32(fields[1].out_value, 0, 5, eice_regs[EICE_COMMS_DATA].addr); + fields[1].out_value[0] = eice_regs[EICE_COMMS_DATA].addr; fields[1].in_value = NULL; fields[2].tap = jtag_info->tap; fields[2].num_bits = 1; fields[2].out_value = field2_out; - buf_set_u32(fields[2].out_value, 0, 1, 0); + fields[2].out_value[0] = 0; fields[2].in_value = NULL; jtag_add_dr_scan(3, fields, jtag_get_end_state()); @@ -431,8 +437,7 @@ int embeddedice_receive(arm_jtag_t *jtag_info, uint32_t *data, uint32_t size) * to avoid reading additional data from the DCC data reg */ if (size == 1) - buf_set_u32(fields[1].out_value, 0, 5, - eice_regs[EICE_COMMS_CTRL].addr); + fields[1].out_value[0] = eice_regs[EICE_COMMS_CTRL].addr; fields[0].in_value = (uint8_t *)data; jtag_add_dr_scan(3, fields, jtag_get_end_state()); @@ -449,7 +454,7 @@ int embeddedice_receive(arm_jtag_t *jtag_info, uint32_t *data, uint32_t size) * Queue a read for an EmbeddedICE register into the register cache, * not checking the value read. */ -int embeddedice_read_reg(reg_t *reg) +int embeddedice_read_reg(struct reg *reg) { return embeddedice_read_reg_w_check(reg, NULL, NULL); } @@ -458,7 +463,7 @@ int embeddedice_read_reg(reg_t *reg) * Queue a write for an EmbeddedICE register, updating the register cache. * Uses embeddedice_write_reg(). */ -void embeddedice_set_reg(reg_t *reg, uint32_t value) +void embeddedice_set_reg(struct reg *reg, uint32_t value) { embeddedice_write_reg(reg, value); @@ -472,7 +477,7 @@ void embeddedice_set_reg(reg_t *reg, uint32_t value) * Write an EmbeddedICE register, updating the register cache. * Uses embeddedice_set_reg(); not queued. */ -int embeddedice_set_reg_w_exec(reg_t *reg, uint8_t *buf) +int embeddedice_set_reg_w_exec(struct reg *reg, uint8_t *buf) { int retval; @@ -485,9 +490,9 @@ int embeddedice_set_reg_w_exec(reg_t *reg, uint8_t *buf) /** * Queue a write for an EmbeddedICE register, bypassing the register cache. */ -void embeddedice_write_reg(reg_t *reg, uint32_t value) +void embeddedice_write_reg(struct reg *reg, uint32_t value) { - embeddedice_reg_t *ice_reg = reg->arch_info; + struct embeddedice_reg *ice_reg = reg->arch_info; LOG_DEBUG("%i: 0x%8.8" PRIx32 "", ice_reg->addr, value); @@ -504,7 +509,7 @@ void embeddedice_write_reg(reg_t *reg, uint32_t value) * Queue a write for an EmbeddedICE register, using cached value. * Uses embeddedice_write_reg(). */ -void embeddedice_store_reg(reg_t *reg) +void embeddedice_store_reg(struct reg *reg) { embeddedice_write_reg(reg, buf_get_u32(reg->value, 0, reg->size)); } @@ -517,7 +522,7 @@ void embeddedice_store_reg(reg_t *reg) * functional clock, so the 50+ JTAG clocks needed to receive the word * allow hundreds of instruction cycles (per word) in the target. */ -int embeddedice_send(arm_jtag_t *jtag_info, uint32_t *data, uint32_t size) +int embeddedice_send(struct arm_jtag *jtag_info, uint32_t *data, uint32_t size) { struct scan_field fields[3]; uint8_t field0_out[4]; @@ -536,13 +541,13 @@ int embeddedice_send(arm_jtag_t *jtag_info, uint32_t *data, uint32_t size) fields[1].tap = jtag_info->tap; fields[1].num_bits = 5; fields[1].out_value = field1_out; - buf_set_u32(fields[1].out_value, 0, 5, eice_regs[EICE_COMMS_DATA].addr); + fields[1].out_value[0] = eice_regs[EICE_COMMS_DATA].addr; fields[1].in_value = NULL; fields[2].tap = jtag_info->tap; fields[2].num_bits = 1; fields[2].out_value = field2_out; - buf_set_u32(fields[2].out_value, 0, 1, 1); + fields[2].out_value[0] = 1; fields[2].in_value = NULL; @@ -562,7 +567,7 @@ int embeddedice_send(arm_jtag_t *jtag_info, uint32_t *data, uint32_t size) /** * Poll DCC control register until read or write handshake completes. */ -int embeddedice_handshake(arm_jtag_t *jtag_info, int hsbit, uint32_t timeout) +int embeddedice_handshake(struct arm_jtag *jtag_info, int hsbit, uint32_t timeout) { struct scan_field fields[3]; uint8_t field0_in[4]; @@ -592,13 +597,13 @@ int embeddedice_handshake(arm_jtag_t *jtag_info, int hsbit, uint32_t timeout) fields[1].tap = jtag_info->tap; fields[1].num_bits = 5; fields[1].out_value = field1_out; - buf_set_u32(fields[1].out_value, 0, 5, eice_regs[EICE_COMMS_DATA].addr); + fields[1].out_value[0] = eice_regs[EICE_COMMS_DATA].addr; fields[1].in_value = NULL; fields[2].tap = jtag_info->tap; fields[2].num_bits = 1; fields[2].out_value = field2_out; - buf_set_u32(fields[2].out_value, 0, 1, 0); + fields[2].out_value[0] = 0; fields[2].in_value = NULL; jtag_add_dr_scan(3, fields, jtag_get_end_state());