X-Git-Url: https://review.openocd.org/gitweb?a=blobdiff_plain;f=src%2Ftarget%2Fembeddedice.c;h=b61df8b0032f4424fb81412d08cabf0755e4d8fe;hb=d86100261252805215282b17d214c48021ef7f79;hp=aa5aacec4c529aa685b28ca618e73ac19e9452e3;hpb=391e1b0a57a5308391c2cb3dae18141ee7535ee8;p=openocd.git

diff --git a/src/target/embeddedice.c b/src/target/embeddedice.c
index aa5aacec4c..b61df8b003 100644
--- a/src/target/embeddedice.c
+++ b/src/target/embeddedice.c
@@ -29,18 +29,6 @@
 
 #include "embeddedice.h"
 
-#include "armv4_5.h"
-#include "arm7_9_common.h"
-
-#include "log.h"
-#include "arm_jtag.h"
-#include "types.h"
-#include "binarybuffer.h"
-#include "target.h"
-#include "register.h"
-#include "jtag.h"
-
-#include <stdlib.h>
 
 #if 0
 static bitfield_desc_t embeddedice_comms_ctrl_bitfield_desc[] =
@@ -191,6 +179,13 @@ reg_cache_t* embeddedice_build_reg_cache(target_t *target, arm7_9_common_t *arm7
 			arm7_9->has_monitor_mode = 1;
 			break;
 		default:
+			/*
+			 * The Feroceon implementation has the version number
+			 * in some unusual bits.  Let feroceon.c validate it
+			 * and do the appropriate setup itself.
+			 */
+			if (strcmp(target_get_name(target), "feroceon") == 0)
+				break;
 			LOG_ERROR("unknown EmbeddedICE version (comms ctrl: 0x%8.8x)", buf_get_u32(reg_list[EICE_COMMS_CTRL].value, 0, 32));
 	}
 
@@ -243,7 +238,7 @@ int embeddedice_read_reg_w_check(reg_t *reg, u8* check_value, u8* check_mask)
 	u8 field1_out[1];
 	u8 field2_out[1];
 
-	jtag_add_end_state(TAP_IDLE);
+	jtag_set_end_state(TAP_IDLE);
 	arm_jtag_scann(ice_reg->jtag_info, 0x2);
 
 	arm_jtag_set_instr(ice_reg->jtag_info, ice_reg->jtag_info->intest_instr, NULL);
@@ -251,39 +246,31 @@ int embeddedice_read_reg_w_check(reg_t *reg, u8* check_value, u8* check_mask)
 	fields[0].tap = ice_reg->jtag_info->tap;
 	fields[0].num_bits = 32;
 	fields[0].out_value = reg->value;
-
 	fields[0].in_value = NULL;
-
-
-	fields[0].in_handler = NULL;
-
+	fields[0].check_value = NULL;
+	fields[0].check_mask = NULL;
 
 	fields[1].tap = ice_reg->jtag_info->tap;
 	fields[1].num_bits = 5;
 	fields[1].out_value = field1_out;
 	buf_set_u32(fields[1].out_value, 0, 5, reg_addr);
-
 	fields[1].in_value = NULL;
-
-
-	fields[1].in_handler = NULL;
-
+	fields[1].check_value = NULL;
+	fields[1].check_mask = NULL;
 
 	fields[2].tap = ice_reg->jtag_info->tap;
 	fields[2].num_bits = 1;
 	fields[2].out_value = field2_out;
 	buf_set_u32(fields[2].out_value, 0, 1, 0);
-
 	fields[2].in_value = NULL;
+	fields[2].check_value = NULL;
+	fields[2].check_mask = NULL;
 
-
-	fields[2].in_handler = NULL;
-
-
-	jtag_add_dr_scan(3, fields, TAP_INVALID);
+	jtag_add_dr_scan(3, fields, jtag_get_end_state());
 
 	fields[0].in_value = reg->value;
-	jtag_set_check_value(fields+0, check_value, check_mask, NULL);
+	fields[0].check_value = check_value;
+	fields[0].check_mask = check_mask;
 
 	/* when reading the DCC data register, leaving the address field set to
 	 * EICE_COMMS_DATA would read the register twice
@@ -291,7 +278,7 @@ int embeddedice_read_reg_w_check(reg_t *reg, u8* check_value, u8* check_mask)
 	 */
 	buf_set_u32(fields[1].out_value, 0, 5, embeddedice_reg_arch_info[EICE_COMMS_CTRL]);
 
-	jtag_add_dr_scan(3, fields, TAP_INVALID);
+	jtag_add_dr_scan_check(3, fields, jtag_get_end_state());
 
 	return ERROR_OK;
 }
@@ -306,32 +293,28 @@ int embeddedice_receive(arm_jtag_t *jtag_info, u32 *data, u32 size)
 	u8 field1_out[1];
 	u8 field2_out[1];
 
-	jtag_add_end_state(TAP_IDLE);
+	jtag_set_end_state(TAP_IDLE);
 	arm_jtag_scann(jtag_info, 0x2);
 	arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL);
 
 	fields[0].tap = jtag_info->tap;
 	fields[0].num_bits = 32;
 	fields[0].out_value = NULL;
-	u8 tmp[4];
-	fields[0].in_value = tmp;
-	fields[0].in_handler = NULL;
+	fields[0].in_value = NULL;
 
 	fields[1].tap = jtag_info->tap;
 	fields[1].num_bits = 5;
 	fields[1].out_value = field1_out;
 	buf_set_u32(fields[1].out_value, 0, 5, embeddedice_reg_arch_info[EICE_COMMS_DATA]);
 	fields[1].in_value = NULL;
-	fields[1].in_handler = NULL;
 
 	fields[2].tap = jtag_info->tap;
 	fields[2].num_bits = 1;
 	fields[2].out_value = field2_out;
 	buf_set_u32(fields[2].out_value, 0, 1, 0);
 	fields[2].in_value = NULL;
-	fields[2].in_handler = NULL;
 
-	jtag_add_dr_scan(3, fields, TAP_INVALID);
+	jtag_add_dr_scan(3, fields, jtag_get_end_state());
 
 	while (size > 0)
 	{
@@ -341,9 +324,9 @@ int embeddedice_receive(arm_jtag_t *jtag_info, u32 *data, u32 size)
 		if (size == 1)
 			buf_set_u32(fields[1].out_value, 0, 5, embeddedice_reg_arch_info[EICE_COMMS_CTRL]);
 
-		jtag_add_dr_scan_now(3, fields, TAP_INVALID);
-
-		*data = le_to_h_u32(tmp);
+		fields[0].in_value = (u8 *)data;
+		jtag_add_dr_scan(3, fields, jtag_get_end_state());
+		jtag_add_callback(arm_le_to_h_u32, (u8 *)data);
 
 		data++;
 		size--;
@@ -386,7 +369,7 @@ void embeddedice_write_reg(reg_t *reg, u32 value)
 
 	LOG_DEBUG("%i: 0x%8.8x", ice_reg->addr, value);
 
-	jtag_add_end_state(TAP_IDLE);
+	jtag_set_end_state(TAP_IDLE);
 	arm_jtag_scann(ice_reg->jtag_info, 0x2);
 
 	arm_jtag_set_instr(ice_reg->jtag_info, ice_reg->jtag_info->intest_instr, NULL);
@@ -412,31 +395,21 @@ int embeddedice_send(arm_jtag_t *jtag_info, u32 *data, u32 size)
 	u8 field1_out[1];
 	u8 field2_out[1];
 
-	jtag_add_end_state(TAP_IDLE);
+	jtag_set_end_state(TAP_IDLE);
 	arm_jtag_scann(jtag_info, 0x2);
 	arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL);
 
 	fields[0].tap = jtag_info->tap;
 	fields[0].num_bits = 32;
 	fields[0].out_value = field0_out;
-
 	fields[0].in_value = NULL;
 
-
-	fields[0].in_handler = NULL;
-
-
 	fields[1].tap = jtag_info->tap;
 	fields[1].num_bits = 5;
 	fields[1].out_value = field1_out;
 	buf_set_u32(fields[1].out_value, 0, 5, embeddedice_reg_arch_info[EICE_COMMS_DATA]);
-
 	fields[1].in_value = NULL;
 
-
-	fields[1].in_handler = NULL;
-
-
 	fields[2].tap = jtag_info->tap;
 	fields[2].num_bits = 1;
 	fields[2].out_value = field2_out;
@@ -444,14 +417,10 @@ int embeddedice_send(arm_jtag_t *jtag_info, u32 *data, u32 size)
 
 	fields[2].in_value = NULL;
 
-
-	fields[2].in_handler = NULL;
-
-
 	while (size > 0)
 	{
 		buf_set_u32(fields[0].out_value, 0, 32, *data);
-		jtag_add_dr_scan(3, fields, TAP_INVALID);
+		jtag_add_dr_scan(3, fields, jtag_get_end_state());
 
 		data++;
 		size--;
@@ -481,47 +450,32 @@ int embeddedice_handshake(arm_jtag_t *jtag_info, int hsbit, u32 timeout)
 	else
 		return ERROR_INVALID_ARGUMENTS;
 
-	jtag_add_end_state(TAP_IDLE);
+	jtag_set_end_state(TAP_IDLE);
 	arm_jtag_scann(jtag_info, 0x2);
 	arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL);
 
 	fields[0].tap = jtag_info->tap;
 	fields[0].num_bits = 32;
 	fields[0].out_value = NULL;
-
 	fields[0].in_value = field0_in;
 
-
-	fields[0].in_handler = NULL;
-
-
 	fields[1].tap = jtag_info->tap;
 	fields[1].num_bits = 5;
 	fields[1].out_value = field1_out;
 	buf_set_u32(fields[1].out_value, 0, 5, embeddedice_reg_arch_info[EICE_COMMS_CTRL]);
-
 	fields[1].in_value = NULL;
 
-
-	fields[1].in_handler = NULL;
-
-
 	fields[2].tap = jtag_info->tap;
 	fields[2].num_bits = 1;
 	fields[2].out_value = field2_out;
 	buf_set_u32(fields[2].out_value, 0, 1, 0);
-
 	fields[2].in_value = NULL;
 
-
-	fields[2].in_handler = NULL;
-
-
-	jtag_add_dr_scan(3, fields, TAP_INVALID);
+	jtag_add_dr_scan(3, fields, jtag_get_end_state());
 	gettimeofday(&lap, NULL);
 	do
 	{
-		jtag_add_dr_scan(3, fields, TAP_INVALID);
+		jtag_add_dr_scan(3, fields, jtag_get_end_state());
 		if ((retval = jtag_execute_queue()) != ERROR_OK)
 			return retval;
 
@@ -535,8 +489,9 @@ int embeddedice_handshake(arm_jtag_t *jtag_info, int hsbit, u32 timeout)
 	return ERROR_TARGET_TIMEOUT;
 }
 
+#ifndef HAVE_JTAG_MINIDRIVER_H
 /* this is the inner loop of the open loop DCC write of data to target */
-void MINIDRIVER(embeddedice_write_dcc)(jtag_tap_t *tap, int reg_addr, u8 *buffer, int little, int count)
+void embeddedice_write_dcc(jtag_tap_t *tap, int reg_addr, u8 *buffer, int little, int count)
 {
 	int i;
 	for (i = 0; i < count; i++)
@@ -545,3 +500,6 @@ void MINIDRIVER(embeddedice_write_dcc)(jtag_tap_t *tap, int reg_addr, u8 *buffer
 		buffer += 4;
 	}
 }
+#else
+/* provided by minidriver */
+#endif