X-Git-Url: https://review.openocd.org/gitweb?a=blobdiff_plain;f=src%2Ftarget%2Fembeddedice.c;h=b61df8b0032f4424fb81412d08cabf0755e4d8fe;hb=d86100261252805215282b17d214c48021ef7f79;hp=883254fc6495941e980af75cee53f965828bfc15;hpb=68c598e88d5e09728ea845a81ab279c615bbaf0f;p=openocd.git diff --git a/src/target/embeddedice.c b/src/target/embeddedice.c index 883254fc64..b61df8b003 100644 --- a/src/target/embeddedice.c +++ b/src/target/embeddedice.c @@ -29,28 +29,18 @@ #include "embeddedice.h" -#include "armv4_5.h" -#include "arm7_9_common.h" -#include "log.h" -#include "arm_jtag.h" -#include "types.h" -#include "binarybuffer.h" -#include "target.h" -#include "register.h" -#include "jtag.h" - -#include - -bitfield_desc_t embeddedice_comms_ctrl_bitfield_desc[] = +#if 0 +static bitfield_desc_t embeddedice_comms_ctrl_bitfield_desc[] = { {"R", 1}, {"W", 1}, {"reserved", 26}, {"version", 4} }; +#endif -int embeddedice_reg_arch_info[] = +static int embeddedice_reg_arch_info[] = { 0x0, 0x1, 0x4, 0x5, 0x8, 0x9, 0xa, 0xb, 0xc, 0xd, @@ -58,7 +48,7 @@ int embeddedice_reg_arch_info[] = 0x2 }; -char* embeddedice_reg_list[] = +static char* embeddedice_reg_list[] = { "debug_ctrl", "debug_status", @@ -83,14 +73,9 @@ char* embeddedice_reg_list[] = "vector catch" }; -int embeddedice_reg_arch_type = -1; +static int embeddedice_reg_arch_type = -1; -int embeddedice_get_reg(reg_t *reg); -int embeddedice_set_reg(reg_t *reg, u32 value); -int embeddedice_set_reg_w_exec(reg_t *reg, u8 *buf); - -int embeddedice_write_reg(reg_t *reg, u32 value); -int embeddedice_read_reg(reg_t *reg); +static int embeddedice_get_reg(reg_t *reg); reg_cache_t* embeddedice_build_reg_cache(target_t *target, arm7_9_common_t *arm7_9) { @@ -194,6 +179,13 @@ reg_cache_t* embeddedice_build_reg_cache(target_t *target, arm7_9_common_t *arm7 arm7_9->has_monitor_mode = 1; break; default: + /* + * The Feroceon implementation has the version number + * in some unusual bits. Let feroceon.c validate it + * and do the appropriate setup itself. + */ + if (strcmp(target_get_name(target), "feroceon") == 0) + break; LOG_ERROR("unknown EmbeddedICE version (comms ctrl: 0x%8.8x)", buf_get_u32(reg_list[EICE_COMMS_CTRL].value, 0, 32)); } @@ -220,17 +212,19 @@ int embeddedice_setup(target_t *target) return jtag_execute_queue(); } -int embeddedice_get_reg(reg_t *reg) +static int embeddedice_get_reg(reg_t *reg) { - if (embeddedice_read_reg(reg) != ERROR_OK) + int retval; + if ((retval = embeddedice_read_reg(reg)) != ERROR_OK) { LOG_ERROR("BUG: error scheduling EmbeddedICE register read"); - exit(-1); + return retval; } - if (jtag_execute_queue() != ERROR_OK) + if ((retval = jtag_execute_queue()) != ERROR_OK) { LOG_ERROR("register read failed"); + return retval; } return ERROR_OK; @@ -244,47 +238,39 @@ int embeddedice_read_reg_w_check(reg_t *reg, u8* check_value, u8* check_mask) u8 field1_out[1]; u8 field2_out[1]; - jtag_add_end_state(TAP_RTI); + jtag_set_end_state(TAP_IDLE); arm_jtag_scann(ice_reg->jtag_info, 0x2); arm_jtag_set_instr(ice_reg->jtag_info, ice_reg->jtag_info->intest_instr, NULL); - fields[0].device = ice_reg->jtag_info->chain_pos; + fields[0].tap = ice_reg->jtag_info->tap; fields[0].num_bits = 32; fields[0].out_value = reg->value; - fields[0].out_mask = NULL; fields[0].in_value = NULL; - fields[0].in_check_value = NULL; - fields[0].in_check_mask = NULL; - fields[0].in_handler = NULL; - fields[0].in_handler_priv = NULL; + fields[0].check_value = NULL; + fields[0].check_mask = NULL; - fields[1].device = ice_reg->jtag_info->chain_pos; + fields[1].tap = ice_reg->jtag_info->tap; fields[1].num_bits = 5; fields[1].out_value = field1_out; buf_set_u32(fields[1].out_value, 0, 5, reg_addr); - fields[1].out_mask = NULL; fields[1].in_value = NULL; - fields[1].in_check_value = NULL; - fields[1].in_check_mask = NULL; - fields[1].in_handler = NULL; - fields[1].in_handler_priv = NULL; + fields[1].check_value = NULL; + fields[1].check_mask = NULL; - fields[2].device = ice_reg->jtag_info->chain_pos; + fields[2].tap = ice_reg->jtag_info->tap; fields[2].num_bits = 1; fields[2].out_value = field2_out; buf_set_u32(fields[2].out_value, 0, 1, 0); - fields[2].out_mask = NULL; fields[2].in_value = NULL; - fields[2].in_check_value = NULL; - fields[2].in_check_mask = NULL; - fields[2].in_handler = NULL; - fields[2].in_handler_priv = NULL; + fields[2].check_value = NULL; + fields[2].check_mask = NULL; - jtag_add_dr_scan(3, fields, -1); + jtag_add_dr_scan(3, fields, jtag_get_end_state()); fields[0].in_value = reg->value; - jtag_set_check_value(fields+0, check_value, check_mask, NULL); + fields[0].check_value = check_value; + fields[0].check_mask = check_mask; /* when reading the DCC data register, leaving the address field set to * EICE_COMMS_DATA would read the register twice @@ -292,7 +278,7 @@ int embeddedice_read_reg_w_check(reg_t *reg, u8* check_value, u8* check_mask) */ buf_set_u32(fields[1].out_value, 0, 5, embeddedice_reg_arch_info[EICE_COMMS_CTRL]); - jtag_add_dr_scan(3, fields, -1); + jtag_add_dr_scan_check(3, fields, jtag_get_end_state()); return ERROR_OK; } @@ -307,43 +293,28 @@ int embeddedice_receive(arm_jtag_t *jtag_info, u32 *data, u32 size) u8 field1_out[1]; u8 field2_out[1]; - jtag_add_end_state(TAP_RTI); + jtag_set_end_state(TAP_IDLE); arm_jtag_scann(jtag_info, 0x2); arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL); - fields[0].device = jtag_info->chain_pos; + fields[0].tap = jtag_info->tap; fields[0].num_bits = 32; fields[0].out_value = NULL; - fields[0].out_mask = NULL; fields[0].in_value = NULL; - fields[0].in_check_value = NULL; - fields[0].in_check_mask = NULL; - fields[0].in_handler = NULL; - fields[0].in_handler_priv = NULL; - fields[1].device = jtag_info->chain_pos; + fields[1].tap = jtag_info->tap; fields[1].num_bits = 5; fields[1].out_value = field1_out; buf_set_u32(fields[1].out_value, 0, 5, embeddedice_reg_arch_info[EICE_COMMS_DATA]); - fields[1].out_mask = NULL; fields[1].in_value = NULL; - fields[1].in_check_value = NULL; - fields[1].in_check_mask = NULL; - fields[1].in_handler = NULL; - fields[1].in_handler_priv = NULL; - fields[2].device = jtag_info->chain_pos; + fields[2].tap = jtag_info->tap; fields[2].num_bits = 1; fields[2].out_value = field2_out; buf_set_u32(fields[2].out_value, 0, 1, 0); - fields[2].out_mask = NULL; fields[2].in_value = NULL; - fields[2].in_check_value = NULL; - fields[2].in_check_mask = NULL; - fields[2].in_handler = NULL; - fields[2].in_handler_priv = NULL; - jtag_add_dr_scan(3, fields, -1); + jtag_add_dr_scan(3, fields, jtag_get_end_state()); while (size > 0) { @@ -353,9 +324,9 @@ int embeddedice_receive(arm_jtag_t *jtag_info, u32 *data, u32 size) if (size == 1) buf_set_u32(fields[1].out_value, 0, 5, embeddedice_reg_arch_info[EICE_COMMS_CTRL]); - fields[0].in_handler = arm_jtag_buf_to_u32; - fields[0].in_handler_priv = data; - jtag_add_dr_scan(3, fields, -1); + fields[0].in_value = (u8 *)data; + jtag_add_dr_scan(3, fields, jtag_get_end_state()); + jtag_add_callback(arm_le_to_h_u32, (u8 *)data); data++; size--; @@ -369,53 +340,48 @@ int embeddedice_read_reg(reg_t *reg) return embeddedice_read_reg_w_check(reg, NULL, NULL); } -int embeddedice_set_reg(reg_t *reg, u32 value) +void embeddedice_set_reg(reg_t *reg, u32 value) { - if (embeddedice_write_reg(reg, value) != ERROR_OK) - { - LOG_ERROR("BUG: error scheduling EmbeddedICE register write"); - exit(-1); - } + embeddedice_write_reg(reg, value); buf_set_u32(reg->value, 0, reg->size, value); reg->valid = 1; reg->dirty = 0; - return ERROR_OK; } int embeddedice_set_reg_w_exec(reg_t *reg, u8 *buf) { + int retval; embeddedice_set_reg(reg, buf_get_u32(buf, 0, reg->size)); - if (jtag_execute_queue() != ERROR_OK) + if ((retval = jtag_execute_queue()) != ERROR_OK) { LOG_ERROR("register write failed"); - exit(-1); + return retval; } return ERROR_OK; } -int embeddedice_write_reg(reg_t *reg, u32 value) +void embeddedice_write_reg(reg_t *reg, u32 value) { embeddedice_reg_t *ice_reg = reg->arch_info; LOG_DEBUG("%i: 0x%8.8x", ice_reg->addr, value); - jtag_add_end_state(TAP_RTI); + jtag_set_end_state(TAP_IDLE); arm_jtag_scann(ice_reg->jtag_info, 0x2); arm_jtag_set_instr(ice_reg->jtag_info, ice_reg->jtag_info->intest_instr, NULL); u8 reg_addr = ice_reg->addr & 0x1f; - embeddedice_write_reg_inner(ice_reg->jtag_info->chain_pos, reg_addr, value); + embeddedice_write_reg_inner(ice_reg->jtag_info->tap, reg_addr, value); - return ERROR_OK; } -int embeddedice_store_reg(reg_t *reg) +void embeddedice_store_reg(reg_t *reg) { - return embeddedice_write_reg(reg, buf_get_u32(reg->value, 0, reg->size)); + embeddedice_write_reg(reg, buf_get_u32(reg->value, 0, reg->size)); } /* send words of 32 bit to the DCC @@ -429,46 +395,32 @@ int embeddedice_send(arm_jtag_t *jtag_info, u32 *data, u32 size) u8 field1_out[1]; u8 field2_out[1]; - jtag_add_end_state(TAP_RTI); + jtag_set_end_state(TAP_IDLE); arm_jtag_scann(jtag_info, 0x2); arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL); - fields[0].device = jtag_info->chain_pos; + fields[0].tap = jtag_info->tap; fields[0].num_bits = 32; fields[0].out_value = field0_out; - fields[0].out_mask = NULL; fields[0].in_value = NULL; - fields[0].in_check_value = NULL; - fields[0].in_check_mask = NULL; - fields[0].in_handler = NULL; - fields[0].in_handler_priv = NULL; - fields[1].device = jtag_info->chain_pos; + fields[1].tap = jtag_info->tap; fields[1].num_bits = 5; fields[1].out_value = field1_out; buf_set_u32(fields[1].out_value, 0, 5, embeddedice_reg_arch_info[EICE_COMMS_DATA]); - fields[1].out_mask = NULL; fields[1].in_value = NULL; - fields[1].in_check_value = NULL; - fields[1].in_check_mask = NULL; - fields[1].in_handler = NULL; - fields[1].in_handler_priv = NULL; - fields[2].device = jtag_info->chain_pos; + fields[2].tap = jtag_info->tap; fields[2].num_bits = 1; fields[2].out_value = field2_out; buf_set_u32(fields[2].out_value, 0, 1, 1); - fields[2].out_mask = NULL; + fields[2].in_value = NULL; - fields[2].in_check_value = NULL; - fields[2].in_check_mask = NULL; - fields[2].in_handler = NULL; - fields[2].in_handler_priv = NULL; while (size > 0) { buf_set_u32(fields[0].out_value, 0, 32, *data); - jtag_add_dr_scan(3, fields, -1); + jtag_add_dr_scan(3, fields, jtag_get_end_state()); data++; size--; @@ -487,7 +439,7 @@ int embeddedice_handshake(arm_jtag_t *jtag_info, int hsbit, u32 timeout) u8 field1_out[1]; u8 field2_out[1]; int retval; - int hsact; + u32 hsact; struct timeval lap; struct timeval now; @@ -498,47 +450,32 @@ int embeddedice_handshake(arm_jtag_t *jtag_info, int hsbit, u32 timeout) else return ERROR_INVALID_ARGUMENTS; - jtag_add_end_state(TAP_RTI); + jtag_set_end_state(TAP_IDLE); arm_jtag_scann(jtag_info, 0x2); arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL); - fields[0].device = jtag_info->chain_pos; + fields[0].tap = jtag_info->tap; fields[0].num_bits = 32; fields[0].out_value = NULL; - fields[0].out_mask = NULL; fields[0].in_value = field0_in; - fields[0].in_check_value = NULL; - fields[0].in_check_mask = NULL; - fields[0].in_handler = NULL; - fields[0].in_handler_priv = NULL; - fields[1].device = jtag_info->chain_pos; + fields[1].tap = jtag_info->tap; fields[1].num_bits = 5; fields[1].out_value = field1_out; buf_set_u32(fields[1].out_value, 0, 5, embeddedice_reg_arch_info[EICE_COMMS_CTRL]); - fields[1].out_mask = NULL; fields[1].in_value = NULL; - fields[1].in_check_value = NULL; - fields[1].in_check_mask = NULL; - fields[1].in_handler = NULL; - fields[1].in_handler_priv = NULL; - fields[2].device = jtag_info->chain_pos; + fields[2].tap = jtag_info->tap; fields[2].num_bits = 1; fields[2].out_value = field2_out; buf_set_u32(fields[2].out_value, 0, 1, 0); - fields[2].out_mask = NULL; fields[2].in_value = NULL; - fields[2].in_check_value = NULL; - fields[2].in_check_mask = NULL; - fields[2].in_handler = NULL; - fields[2].in_handler_priv = NULL; - jtag_add_dr_scan(3, fields, -1); + jtag_add_dr_scan(3, fields, jtag_get_end_state()); gettimeofday(&lap, NULL); do { - jtag_add_dr_scan(3, fields, -1); + jtag_add_dr_scan(3, fields, jtag_get_end_state()); if ((retval = jtag_execute_queue()) != ERROR_OK) return retval; @@ -547,18 +484,22 @@ int embeddedice_handshake(arm_jtag_t *jtag_info, int hsbit, u32 timeout) gettimeofday(&now, NULL); } - while ((now.tv_sec-lap.tv_sec)*1000 + (now.tv_usec-lap.tv_usec)/1000 <= timeout); + while ((u32)((now.tv_sec-lap.tv_sec)*1000 + (now.tv_usec-lap.tv_usec)/1000) <= timeout); return ERROR_TARGET_TIMEOUT; } +#ifndef HAVE_JTAG_MINIDRIVER_H /* this is the inner loop of the open loop DCC write of data to target */ -void MINIDRIVER(embeddedice_write_dcc)(int chain_pos, int reg_addr, u8 *buffer, int little, int count) +void embeddedice_write_dcc(jtag_tap_t *tap, int reg_addr, u8 *buffer, int little, int count) { int i; for (i = 0; i < count; i++) { - embeddedice_write_reg_inner(chain_pos, reg_addr, fast_target_buffer_get_u32(buffer, little)); + embeddedice_write_reg_inner(tap, reg_addr, fast_target_buffer_get_u32(buffer, little)); buffer += 4; } } +#else +/* provided by minidriver */ +#endif