X-Git-Url: https://review.openocd.org/gitweb?a=blobdiff_plain;f=src%2Ftarget%2Fembeddedice.c;h=5f99120b9a9bebc6d3737cf4a9295c4ef145c995;hb=84df52f9ea78e2d71bde648a16b69d80404c6421;hp=cfe4ed7c8a74194bd806264935d5dc1acc123084;hpb=e86dee32004d750e8654fe449bfcdffaed7339fa;p=openocd.git

diff --git a/src/target/embeddedice.c b/src/target/embeddedice.c
index cfe4ed7c8a..5f99120b9a 100644
--- a/src/target/embeddedice.c
+++ b/src/target/embeddedice.c
@@ -29,18 +29,6 @@
 
 #include "embeddedice.h"
 
-#include "armv4_5.h"
-#include "arm7_9_common.h"
-
-#include "log.h"
-#include "arm_jtag.h"
-#include "types.h"
-#include "binarybuffer.h"
-#include "target.h"
-#include "register.h"
-#include "jtag.h"
-
-#include <stdlib.h>
 
 #if 0
 static bitfield_desc_t embeddedice_comms_ctrl_bitfield_desc[] =
@@ -137,7 +125,7 @@ reg_cache_t* embeddedice_build_reg_cache(target_t *target, arm7_9_common_t *arm7
 
 	/* identify EmbeddedICE version by reading DCC control register */
 	embeddedice_read_reg(&reg_list[EICE_COMMS_CTRL]);
-	if ((retval=jtag_execute_queue())!=ERROR_OK)
+	if ((retval = jtag_execute_queue()) != ERROR_OK)
 	{
 		for (i = 0; i < num_regs; i++)
 		{
@@ -191,7 +179,14 @@ reg_cache_t* embeddedice_build_reg_cache(target_t *target, arm7_9_common_t *arm7
 			arm7_9->has_monitor_mode = 1;
 			break;
 		default:
-			LOG_ERROR("unknown EmbeddedICE version (comms ctrl: 0x%8.8x)", buf_get_u32(reg_list[EICE_COMMS_CTRL].value, 0, 32));
+			/*
+			 * The Feroceon implementation has the version number
+			 * in some unusual bits.  Let feroceon.c validate it
+			 * and do the appropriate setup itself.
+			 */
+			if (strcmp(target_get_name(target), "feroceon") == 0)
+				break;
+			LOG_ERROR("unknown EmbeddedICE version (comms ctrl: 0x%8.8" PRIx32 ")", buf_get_u32(reg_list[EICE_COMMS_CTRL].value, 0, 32));
 	}
 
 	return reg_cache;
@@ -209,7 +204,7 @@ int embeddedice_setup(target_t *target)
 		reg_t *dbg_ctrl = &arm7_9->eice_cache->reg_list[EICE_DBG_CTRL];
 
 		embeddedice_read_reg(dbg_ctrl);
-		if ((retval=jtag_execute_queue())!=ERROR_OK)
+		if ((retval = jtag_execute_queue()) != ERROR_OK)
 			return retval;
 		buf_set_u32(dbg_ctrl->value, 4, 1, 0);
 		embeddedice_set_reg_w_exec(dbg_ctrl, dbg_ctrl->value);
@@ -235,15 +230,15 @@ static int embeddedice_get_reg(reg_t *reg)
 	return ERROR_OK;
 }
 
-int embeddedice_read_reg_w_check(reg_t *reg, u8* check_value, u8* check_mask)
+int embeddedice_read_reg_w_check(reg_t *reg, uint8_t* check_value, uint8_t* check_mask)
 {
 	embeddedice_reg_t *ice_reg = reg->arch_info;
-	u8 reg_addr = ice_reg->addr & 0x1f;
+	uint8_t reg_addr = ice_reg->addr & 0x1f;
 	scan_field_t fields[3];
-	u8 field1_out[1];
-	u8 field2_out[1];
+	uint8_t field1_out[1];
+	uint8_t field2_out[1];
 
-	jtag_add_end_state(TAP_IDLE);
+	jtag_set_end_state(TAP_IDLE);
 	arm_jtag_scann(ice_reg->jtag_info, 0x2);
 
 	arm_jtag_set_instr(ice_reg->jtag_info, ice_reg->jtag_info->intest_instr, NULL);
@@ -251,39 +246,31 @@ int embeddedice_read_reg_w_check(reg_t *reg, u8* check_value, u8* check_mask)
 	fields[0].tap = ice_reg->jtag_info->tap;
 	fields[0].num_bits = 32;
 	fields[0].out_value = reg->value;
-	
 	fields[0].in_value = NULL;
-	
-	
-	fields[0].in_handler = NULL;
-	
+	fields[0].check_value = NULL;
+	fields[0].check_mask = NULL;
 
 	fields[1].tap = ice_reg->jtag_info->tap;
 	fields[1].num_bits = 5;
 	fields[1].out_value = field1_out;
 	buf_set_u32(fields[1].out_value, 0, 5, reg_addr);
-	
 	fields[1].in_value = NULL;
-	
-	
-	fields[1].in_handler = NULL;
-	
+	fields[1].check_value = NULL;
+	fields[1].check_mask = NULL;
 
 	fields[2].tap = ice_reg->jtag_info->tap;
 	fields[2].num_bits = 1;
 	fields[2].out_value = field2_out;
 	buf_set_u32(fields[2].out_value, 0, 1, 0);
-	
 	fields[2].in_value = NULL;
-	
-	
-	fields[2].in_handler = NULL;
-	
+	fields[2].check_value = NULL;
+	fields[2].check_mask = NULL;
 
-	jtag_add_dr_scan(3, fields, TAP_INVALID);
+	jtag_add_dr_scan(3, fields, jtag_get_end_state());
 
 	fields[0].in_value = reg->value;
-	jtag_set_check_value(fields+0, check_value, check_mask, NULL);
+	fields[0].check_value = check_value;
+	fields[0].check_mask = check_mask;
 
 	/* when reading the DCC data register, leaving the address field set to
 	 * EICE_COMMS_DATA would read the register twice
@@ -291,7 +278,7 @@ int embeddedice_read_reg_w_check(reg_t *reg, u8* check_value, u8* check_mask)
 	 */
 	buf_set_u32(fields[1].out_value, 0, 5, embeddedice_reg_arch_info[EICE_COMMS_CTRL]);
 
-	jtag_add_dr_scan(3, fields, TAP_INVALID);
+	jtag_add_dr_scan_check(3, fields, jtag_get_end_state());
 
 	return ERROR_OK;
 }
@@ -300,49 +287,34 @@ int embeddedice_read_reg_w_check(reg_t *reg, u8* check_value, u8* check_mask)
  * we pretend the target is always going to be fast enough
  * (relative to the JTAG clock), so we don't need to handshake
  */
-int embeddedice_receive(arm_jtag_t *jtag_info, u32 *data, u32 size)
+int embeddedice_receive(arm_jtag_t *jtag_info, uint32_t *data, uint32_t size)
 {
 	scan_field_t fields[3];
-	u8 field1_out[1];
-	u8 field2_out[1];
+	uint8_t field1_out[1];
+	uint8_t field2_out[1];
 
-	jtag_add_end_state(TAP_IDLE);
+	jtag_set_end_state(TAP_IDLE);
 	arm_jtag_scann(jtag_info, 0x2);
 	arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL);
 
 	fields[0].tap = jtag_info->tap;
 	fields[0].num_bits = 32;
 	fields[0].out_value = NULL;
-	
 	fields[0].in_value = NULL;
-	
-	
-	fields[0].in_handler = NULL;
-	
 
 	fields[1].tap = jtag_info->tap;
 	fields[1].num_bits = 5;
 	fields[1].out_value = field1_out;
 	buf_set_u32(fields[1].out_value, 0, 5, embeddedice_reg_arch_info[EICE_COMMS_DATA]);
-	
 	fields[1].in_value = NULL;
-	
-	
-	fields[1].in_handler = NULL;
-	
 
 	fields[2].tap = jtag_info->tap;
 	fields[2].num_bits = 1;
 	fields[2].out_value = field2_out;
 	buf_set_u32(fields[2].out_value, 0, 1, 0);
-	
 	fields[2].in_value = NULL;
-	
-	
-	fields[2].in_handler = NULL;
-	
 
-	jtag_add_dr_scan(3, fields, TAP_INVALID);
+	jtag_add_dr_scan(3, fields, jtag_get_end_state());
 
 	while (size > 0)
 	{
@@ -352,9 +324,9 @@ int embeddedice_receive(arm_jtag_t *jtag_info, u32 *data, u32 size)
 		if (size == 1)
 			buf_set_u32(fields[1].out_value, 0, 5, embeddedice_reg_arch_info[EICE_COMMS_CTRL]);
 
-		fields[0].in_handler = arm_jtag_buf_to_u32; /* deprecated! invoke this from user code! */
-		fields[0].in_handler_priv = data;
-		jtag_add_dr_scan(3, fields, TAP_INVALID);
+		fields[0].in_value = (uint8_t *)data;
+		jtag_add_dr_scan(3, fields, jtag_get_end_state());
+		jtag_add_callback(arm_le_to_h_u32, (jtag_callback_data_t)data);
 
 		data++;
 		size--;
@@ -368,7 +340,7 @@ int embeddedice_read_reg(reg_t *reg)
 	return embeddedice_read_reg_w_check(reg, NULL, NULL);
 }
 
-void embeddedice_set_reg(reg_t *reg, u32 value)
+void embeddedice_set_reg(reg_t *reg, uint32_t value)
 {
 	embeddedice_write_reg(reg, value);
 
@@ -378,7 +350,7 @@ void embeddedice_set_reg(reg_t *reg, u32 value)
 
 }
 
-int embeddedice_set_reg_w_exec(reg_t *reg, u8 *buf)
+int embeddedice_set_reg_w_exec(reg_t *reg, uint8_t *buf)
 {
 	int retval;
 	embeddedice_set_reg(reg, buf_get_u32(buf, 0, reg->size));
@@ -391,18 +363,18 @@ int embeddedice_set_reg_w_exec(reg_t *reg, u8 *buf)
 	return ERROR_OK;
 }
 
-void embeddedice_write_reg(reg_t *reg, u32 value)
+void embeddedice_write_reg(reg_t *reg, uint32_t value)
 {
 	embeddedice_reg_t *ice_reg = reg->arch_info;
 
-	LOG_DEBUG("%i: 0x%8.8x", ice_reg->addr, value);
+	LOG_DEBUG("%i: 0x%8.8" PRIx32 "", ice_reg->addr, value);
 
-	jtag_add_end_state(TAP_IDLE);
+	jtag_set_end_state(TAP_IDLE);
 	arm_jtag_scann(ice_reg->jtag_info, 0x2);
 
 	arm_jtag_set_instr(ice_reg->jtag_info, ice_reg->jtag_info->intest_instr, NULL);
 
-	u8 reg_addr = ice_reg->addr & 0x1f;
+	uint8_t reg_addr = ice_reg->addr & 0x1f;
 	embeddedice_write_reg_inner(ice_reg->jtag_info->tap, reg_addr, value);
 
 }
@@ -416,53 +388,39 @@ void embeddedice_store_reg(reg_t *reg)
  * we pretend the target is always going to be fast enough
  * (relative to the JTAG clock), so we don't need to handshake
  */
-int embeddedice_send(arm_jtag_t *jtag_info, u32 *data, u32 size)
+int embeddedice_send(arm_jtag_t *jtag_info, uint32_t *data, uint32_t size)
 {
 	scan_field_t fields[3];
-	u8 field0_out[4];
-	u8 field1_out[1];
-	u8 field2_out[1];
+	uint8_t field0_out[4];
+	uint8_t field1_out[1];
+	uint8_t field2_out[1];
 
-	jtag_add_end_state(TAP_IDLE);
+	jtag_set_end_state(TAP_IDLE);
 	arm_jtag_scann(jtag_info, 0x2);
 	arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL);
 
 	fields[0].tap = jtag_info->tap;
 	fields[0].num_bits = 32;
 	fields[0].out_value = field0_out;
-	
 	fields[0].in_value = NULL;
-	
-	
-	fields[0].in_handler = NULL;
-	
 
 	fields[1].tap = jtag_info->tap;
 	fields[1].num_bits = 5;
 	fields[1].out_value = field1_out;
 	buf_set_u32(fields[1].out_value, 0, 5, embeddedice_reg_arch_info[EICE_COMMS_DATA]);
-	
 	fields[1].in_value = NULL;
-	
-	
-	fields[1].in_handler = NULL;
-	
 
 	fields[2].tap = jtag_info->tap;
 	fields[2].num_bits = 1;
 	fields[2].out_value = field2_out;
 	buf_set_u32(fields[2].out_value, 0, 1, 1);
-	
+
 	fields[2].in_value = NULL;
-	
-	
-	fields[2].in_handler = NULL;
-	
 
 	while (size > 0)
 	{
 		buf_set_u32(fields[0].out_value, 0, 32, *data);
-		jtag_add_dr_scan(3, fields, TAP_INVALID);
+		jtag_add_dr_scan(3, fields, jtag_get_end_state());
 
 		data++;
 		size--;
@@ -474,14 +432,14 @@ int embeddedice_send(arm_jtag_t *jtag_info, u32 *data, u32 size)
 
 /* wait for DCC control register R/W handshake bit to become active
  */
-int embeddedice_handshake(arm_jtag_t *jtag_info, int hsbit, u32 timeout)
+int embeddedice_handshake(arm_jtag_t *jtag_info, int hsbit, uint32_t timeout)
 {
 	scan_field_t fields[3];
-	u8 field0_in[4];
-	u8 field1_out[1];
-	u8 field2_out[1];
+	uint8_t field0_in[4];
+	uint8_t field1_out[1];
+	uint8_t field2_out[1];
 	int retval;
-	u32 hsact;
+	uint32_t hsact;
 	struct timeval lap;
 	struct timeval now;
 
@@ -492,47 +450,32 @@ int embeddedice_handshake(arm_jtag_t *jtag_info, int hsbit, u32 timeout)
 	else
 		return ERROR_INVALID_ARGUMENTS;
 
-	jtag_add_end_state(TAP_IDLE);
+	jtag_set_end_state(TAP_IDLE);
 	arm_jtag_scann(jtag_info, 0x2);
 	arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL);
 
 	fields[0].tap = jtag_info->tap;
 	fields[0].num_bits = 32;
 	fields[0].out_value = NULL;
-	
 	fields[0].in_value = field0_in;
-	
-	
-	fields[0].in_handler = NULL;
-	
 
 	fields[1].tap = jtag_info->tap;
 	fields[1].num_bits = 5;
 	fields[1].out_value = field1_out;
 	buf_set_u32(fields[1].out_value, 0, 5, embeddedice_reg_arch_info[EICE_COMMS_CTRL]);
-	
 	fields[1].in_value = NULL;
-	
-	
-	fields[1].in_handler = NULL;
-	
 
 	fields[2].tap = jtag_info->tap;
 	fields[2].num_bits = 1;
 	fields[2].out_value = field2_out;
 	buf_set_u32(fields[2].out_value, 0, 1, 0);
-	
 	fields[2].in_value = NULL;
-	
-	
-	fields[2].in_handler = NULL;
-	
 
-	jtag_add_dr_scan(3, fields, TAP_INVALID);
+	jtag_add_dr_scan(3, fields, jtag_get_end_state());
 	gettimeofday(&lap, NULL);
 	do
 	{
-		jtag_add_dr_scan(3, fields, TAP_INVALID);
+		jtag_add_dr_scan(3, fields, jtag_get_end_state());
 		if ((retval = jtag_execute_queue()) != ERROR_OK)
 			return retval;
 
@@ -541,13 +484,14 @@ int embeddedice_handshake(arm_jtag_t *jtag_info, int hsbit, u32 timeout)
 
 		gettimeofday(&now, NULL);
 	}
-	while ((u32)((now.tv_sec-lap.tv_sec)*1000 + (now.tv_usec-lap.tv_usec)/1000) <= timeout);
+	while ((uint32_t)((now.tv_sec-lap.tv_sec)*1000 + (now.tv_usec-lap.tv_usec)/1000) <= timeout);
 
 	return ERROR_TARGET_TIMEOUT;
 }
 
+#ifndef HAVE_JTAG_MINIDRIVER_H
 /* this is the inner loop of the open loop DCC write of data to target */
-void MINIDRIVER(embeddedice_write_dcc)(jtag_tap_t *tap, int reg_addr, u8 *buffer, int little, int count)
+void embeddedice_write_dcc(jtag_tap_t *tap, int reg_addr, uint8_t *buffer, int little, int count)
 {
 	int i;
 	for (i = 0; i < count; i++)
@@ -556,3 +500,6 @@ void MINIDRIVER(embeddedice_write_dcc)(jtag_tap_t *tap, int reg_addr, u8 *buffer
 		buffer += 4;
 	}
 }
+#else
+/* provided by minidriver */
+#endif