X-Git-Url: https://review.openocd.org/gitweb?a=blobdiff_plain;f=src%2Ftarget%2Fembeddedice.c;h=5f99120b9a9bebc6d3737cf4a9295c4ef145c995;hb=84df52f9ea78e2d71bde648a16b69d80404c6421;hp=b61df8b0032f4424fb81412d08cabf0755e4d8fe;hpb=d86100261252805215282b17d214c48021ef7f79;p=openocd.git diff --git a/src/target/embeddedice.c b/src/target/embeddedice.c index b61df8b003..5f99120b9a 100644 --- a/src/target/embeddedice.c +++ b/src/target/embeddedice.c @@ -125,7 +125,7 @@ reg_cache_t* embeddedice_build_reg_cache(target_t *target, arm7_9_common_t *arm7 /* identify EmbeddedICE version by reading DCC control register */ embeddedice_read_reg(®_list[EICE_COMMS_CTRL]); - if ((retval=jtag_execute_queue())!=ERROR_OK) + if ((retval = jtag_execute_queue()) != ERROR_OK) { for (i = 0; i < num_regs; i++) { @@ -186,7 +186,7 @@ reg_cache_t* embeddedice_build_reg_cache(target_t *target, arm7_9_common_t *arm7 */ if (strcmp(target_get_name(target), "feroceon") == 0) break; - LOG_ERROR("unknown EmbeddedICE version (comms ctrl: 0x%8.8x)", buf_get_u32(reg_list[EICE_COMMS_CTRL].value, 0, 32)); + LOG_ERROR("unknown EmbeddedICE version (comms ctrl: 0x%8.8" PRIx32 ")", buf_get_u32(reg_list[EICE_COMMS_CTRL].value, 0, 32)); } return reg_cache; @@ -204,7 +204,7 @@ int embeddedice_setup(target_t *target) reg_t *dbg_ctrl = &arm7_9->eice_cache->reg_list[EICE_DBG_CTRL]; embeddedice_read_reg(dbg_ctrl); - if ((retval=jtag_execute_queue())!=ERROR_OK) + if ((retval = jtag_execute_queue()) != ERROR_OK) return retval; buf_set_u32(dbg_ctrl->value, 4, 1, 0); embeddedice_set_reg_w_exec(dbg_ctrl, dbg_ctrl->value); @@ -230,13 +230,13 @@ static int embeddedice_get_reg(reg_t *reg) return ERROR_OK; } -int embeddedice_read_reg_w_check(reg_t *reg, u8* check_value, u8* check_mask) +int embeddedice_read_reg_w_check(reg_t *reg, uint8_t* check_value, uint8_t* check_mask) { embeddedice_reg_t *ice_reg = reg->arch_info; - u8 reg_addr = ice_reg->addr & 0x1f; + uint8_t reg_addr = ice_reg->addr & 0x1f; scan_field_t fields[3]; - u8 field1_out[1]; - u8 field2_out[1]; + uint8_t field1_out[1]; + uint8_t field2_out[1]; jtag_set_end_state(TAP_IDLE); arm_jtag_scann(ice_reg->jtag_info, 0x2); @@ -287,11 +287,11 @@ int embeddedice_read_reg_w_check(reg_t *reg, u8* check_value, u8* check_mask) * we pretend the target is always going to be fast enough * (relative to the JTAG clock), so we don't need to handshake */ -int embeddedice_receive(arm_jtag_t *jtag_info, u32 *data, u32 size) +int embeddedice_receive(arm_jtag_t *jtag_info, uint32_t *data, uint32_t size) { scan_field_t fields[3]; - u8 field1_out[1]; - u8 field2_out[1]; + uint8_t field1_out[1]; + uint8_t field2_out[1]; jtag_set_end_state(TAP_IDLE); arm_jtag_scann(jtag_info, 0x2); @@ -324,9 +324,9 @@ int embeddedice_receive(arm_jtag_t *jtag_info, u32 *data, u32 size) if (size == 1) buf_set_u32(fields[1].out_value, 0, 5, embeddedice_reg_arch_info[EICE_COMMS_CTRL]); - fields[0].in_value = (u8 *)data; + fields[0].in_value = (uint8_t *)data; jtag_add_dr_scan(3, fields, jtag_get_end_state()); - jtag_add_callback(arm_le_to_h_u32, (u8 *)data); + jtag_add_callback(arm_le_to_h_u32, (jtag_callback_data_t)data); data++; size--; @@ -340,7 +340,7 @@ int embeddedice_read_reg(reg_t *reg) return embeddedice_read_reg_w_check(reg, NULL, NULL); } -void embeddedice_set_reg(reg_t *reg, u32 value) +void embeddedice_set_reg(reg_t *reg, uint32_t value) { embeddedice_write_reg(reg, value); @@ -350,7 +350,7 @@ void embeddedice_set_reg(reg_t *reg, u32 value) } -int embeddedice_set_reg_w_exec(reg_t *reg, u8 *buf) +int embeddedice_set_reg_w_exec(reg_t *reg, uint8_t *buf) { int retval; embeddedice_set_reg(reg, buf_get_u32(buf, 0, reg->size)); @@ -363,18 +363,18 @@ int embeddedice_set_reg_w_exec(reg_t *reg, u8 *buf) return ERROR_OK; } -void embeddedice_write_reg(reg_t *reg, u32 value) +void embeddedice_write_reg(reg_t *reg, uint32_t value) { embeddedice_reg_t *ice_reg = reg->arch_info; - LOG_DEBUG("%i: 0x%8.8x", ice_reg->addr, value); + LOG_DEBUG("%i: 0x%8.8" PRIx32 "", ice_reg->addr, value); jtag_set_end_state(TAP_IDLE); arm_jtag_scann(ice_reg->jtag_info, 0x2); arm_jtag_set_instr(ice_reg->jtag_info, ice_reg->jtag_info->intest_instr, NULL); - u8 reg_addr = ice_reg->addr & 0x1f; + uint8_t reg_addr = ice_reg->addr & 0x1f; embeddedice_write_reg_inner(ice_reg->jtag_info->tap, reg_addr, value); } @@ -388,12 +388,12 @@ void embeddedice_store_reg(reg_t *reg) * we pretend the target is always going to be fast enough * (relative to the JTAG clock), so we don't need to handshake */ -int embeddedice_send(arm_jtag_t *jtag_info, u32 *data, u32 size) +int embeddedice_send(arm_jtag_t *jtag_info, uint32_t *data, uint32_t size) { scan_field_t fields[3]; - u8 field0_out[4]; - u8 field1_out[1]; - u8 field2_out[1]; + uint8_t field0_out[4]; + uint8_t field1_out[1]; + uint8_t field2_out[1]; jtag_set_end_state(TAP_IDLE); arm_jtag_scann(jtag_info, 0x2); @@ -432,14 +432,14 @@ int embeddedice_send(arm_jtag_t *jtag_info, u32 *data, u32 size) /* wait for DCC control register R/W handshake bit to become active */ -int embeddedice_handshake(arm_jtag_t *jtag_info, int hsbit, u32 timeout) +int embeddedice_handshake(arm_jtag_t *jtag_info, int hsbit, uint32_t timeout) { scan_field_t fields[3]; - u8 field0_in[4]; - u8 field1_out[1]; - u8 field2_out[1]; + uint8_t field0_in[4]; + uint8_t field1_out[1]; + uint8_t field2_out[1]; int retval; - u32 hsact; + uint32_t hsact; struct timeval lap; struct timeval now; @@ -484,14 +484,14 @@ int embeddedice_handshake(arm_jtag_t *jtag_info, int hsbit, u32 timeout) gettimeofday(&now, NULL); } - while ((u32)((now.tv_sec-lap.tv_sec)*1000 + (now.tv_usec-lap.tv_usec)/1000) <= timeout); + while ((uint32_t)((now.tv_sec-lap.tv_sec)*1000 + (now.tv_usec-lap.tv_usec)/1000) <= timeout); return ERROR_TARGET_TIMEOUT; } #ifndef HAVE_JTAG_MINIDRIVER_H /* this is the inner loop of the open loop DCC write of data to target */ -void embeddedice_write_dcc(jtag_tap_t *tap, int reg_addr, u8 *buffer, int little, int count) +void embeddedice_write_dcc(jtag_tap_t *tap, int reg_addr, uint8_t *buffer, int little, int count) { int i; for (i = 0; i < count; i++)