X-Git-Url: https://review.openocd.org/gitweb?a=blobdiff_plain;f=src%2Ftarget%2Fcortex_m3.c;h=df00fc19e9ec4fb3e9f64d3b9603311ea58c3b94;hb=56a04a3413a6427ef83dc18e3f7c7c13fd217113;hp=53ecd0a90d5309e89de466efed373f37a438308a;hpb=519896811600849b27f0803e08ee5f9152423f24;p=openocd.git diff --git a/src/target/cortex_m3.c b/src/target/cortex_m3.c index 53ecd0a90d..df00fc19e9 100644 --- a/src/target/cortex_m3.c +++ b/src/target/cortex_m3.c @@ -24,7 +24,7 @@ * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. * * * * * - * Cortex-M3(tm) TRM, ARM DDI 0337C * + * Cortex-M3(tm) TRM, ARM DDI 0337E (r1p1) and 0337G (r2p0) * * * ***************************************************************************/ #ifdef HAVE_CONFIG_H @@ -34,6 +34,10 @@ #include "cortex_m3.h" #include "target_request.h" #include "target_type.h" +#include "arm_disassembler.h" + + +#define ARRAY_SIZE(x) ((int)(sizeof(x)/sizeof((x)[0]))) /* cli handling */ @@ -173,7 +177,7 @@ int cortex_m3_clear_halt(target_t *target) /* Read Debug Fault Status Register */ mem_ap_read_atomic_u32(swjdp, NVIC_DFSR, &cortex_m3->nvic_dfsr); - /* Write Debug Fault Status Register to enable processing to resume ?? Try with and without this !! */ + /* Clear Debug Fault Status */ mem_ap_write_atomic_u32(swjdp, NVIC_DFSR, cortex_m3->nvic_dfsr); LOG_DEBUG(" NVIC_DFSR 0x%" PRIx32 "", cortex_m3->nvic_dfsr); @@ -306,8 +310,6 @@ int cortex_m3_examine_debug_reason(target_t *target) if ((target->debug_reason != DBG_REASON_DBGRQ) && (target->debug_reason != DBG_REASON_SINGLESTEP)) { - /* INCOMPLETE */ - if (cortex_m3->nvic_dfsr & DFSR_BKPT) { target->debug_reason = DBG_REASON_BREAKPOINT; @@ -316,6 +318,10 @@ int cortex_m3_examine_debug_reason(target_t *target) } else if (cortex_m3->nvic_dfsr & DFSR_DWTTRAP) target->debug_reason = DBG_REASON_WATCHPOINT; + else if (cortex_m3->nvic_dfsr & DFSR_VCATCH) + target->debug_reason = DBG_REASON_BREAKPOINT; + else /* EXTERNAL, HALTED, DWTTRAP w/o BKPT */ + target->debug_reason = DBG_REASON_UNDEFINED; } return ERROR_OK; @@ -394,7 +400,9 @@ int cortex_m3_debug_entry(target_t *target) /* Examine target state and mode */ /* First load register acessible through core debug port*/ - for (i = 0; i < ARMV7M_PRIMASK; i++) + int num_regs = armv7m->core_cache->num_regs; + + for (i = 0; i < num_regs; i++) { if (!armv7m->core_cache->reg_list[i].valid) armv7m->read_core_reg(target, i); @@ -417,13 +425,6 @@ int cortex_m3_debug_entry(target_t *target) cortex_m3_store_core_reg_u32(target, ARMV7M_REGISTER_CORE_GP, 16, xPSR &~ 0xff); } - /* Now we can load SP core registers */ - for (i = ARMV7M_PRIMASK; i < ARMV7NUMCOREREGS; i++) - { - if (!armv7m->core_cache->reg_list[i].valid) - armv7m->read_core_reg(target, i); - } - /* Are we in an exception handler */ if (xPSR & 0x1FF) { @@ -759,11 +760,14 @@ int cortex_m3_assert_reset(target_t *target) target_state_name(target)); enum reset_types jtag_reset_config = jtag_get_reset_config(); + + /* + * We can reset Cortex-M3 targets using just the NVIC without + * requiring SRST, getting a SoC reset (or a core-only reset) + * instead of a system reset. + */ if (!(jtag_reset_config & RESET_HAS_SRST)) - { - LOG_ERROR("Can't assert SRST"); - return ERROR_FAIL; - } + assert_srst = 0; /* Enable debug requests */ mem_ap_read_atomic_u32(swjdp, DCB_DHCSR, &cortex_m3->dcb_dhcsr); @@ -793,15 +797,21 @@ int cortex_m3_assert_reset(target_t *target) mem_ap_write_atomic_u32(swjdp, DCB_DEMCR, TRCENA | VC_HARDERR | VC_BUSERR | VC_CORERESET); } - /* following hack is to handle luminary reset - * when srst is asserted the luminary device seesm to also clear the debug registers - * which does not match the armv7 debug TRM */ - + /* + * When nRST is asserted on most Stellaris devices, it clears some of + * the debug state. The ARMv7M and Cortex-M3 TRMs say that's wrong; + * and OpenOCD depends on those TRMs. So we won't use SRST on those + * chips. (Only power-on reset should affect debug state, beyond a + * few specified bits; not the chip's nRST input, wired to SRST.) + * + * REVISIT current errata specs don't seem to cover this issue. + * Do we have more details than this email? + * https://lists.berlios.de/pipermail + * /openocd-development/2008-August/003065.html + */ if (strcmp(target->variant, "lm3s") == 0) { - /* get revision of lm3s target, only early silicon has this issue - * Fury Rev B, DustDevil Rev B, Tempest all ok */ - + /* Check for silicon revisions with the issue. */ uint32_t did0; if (target_read_u32(target, 0x400fe000, &did0) == ERROR_OK) @@ -815,10 +825,16 @@ int cortex_m3_assert_reset(target_t *target) case 1: case 3: - /* only Fury/DustDevil rev A suffer reset problems */ + /* Fury and DustDevil rev A have + * this nRST problem. It should + * be fixed in rev B silicon. + */ if (((did0 >> 8) & 0xff) == 0) assert_srst = 0; break; + case 4: + /* Tempest should be fine. */ + break; } } } @@ -837,13 +853,20 @@ int cortex_m3_assert_reset(target_t *target) } else { - /* this causes the luminary device to reset using the watchdog */ - mem_ap_write_atomic_u32(swjdp, NVIC_AIRCR, AIRCR_VECTKEY | AIRCR_SYSRESETREQ); - LOG_DEBUG("Using Luminary Reset: SYSRESETREQ"); + /* Use a standard Cortex-M3 software reset mechanism. + * SYSRESETREQ will reset SoC peripherals outside the + * core, like watchdog timers, if the SoC wires it up + * correctly. Else VECRESET can reset just the core. + */ + mem_ap_write_atomic_u32(swjdp, NVIC_AIRCR, + AIRCR_VECTKEY | AIRCR_SYSRESETREQ); + LOG_DEBUG("Using Cortex-M3 SYSRESETREQ"); { - /* I do not know why this is necessary, but it fixes strange effects - * (step/resume cause a NMI after reset) on LM3S6918 -- Michael Schwingen */ + /* I do not know why this is necessary, but it + * fixes strange effects (step/resume cause NMI + * after reset) on LM3S6918 -- Michael Schwingen + */ uint32_t tmp; mem_ap_read_atomic_u32(swjdp, NVIC_AIRCR, &tmp); } @@ -1252,8 +1275,12 @@ int cortex_m3_load_core_reg_u32(struct target_s *target, enum armv7m_regtype typ armv7m_common_t *armv7m = target->arch_info; swjdp_common_t *swjdp = &armv7m->swjdp_info; - if ((type == ARMV7M_REGISTER_CORE_GP) && (num <= ARMV7M_PSP)) - { + /* NOTE: we "know" here that the register identifiers used + * in the v7m header match the Cortex-M3 Debug Core Register + * Selector values for R0..R15, xPSR, MSP, and PSP. + */ + switch (num) { + case 0 ... 18: /* read a normal core register */ retval = cortexm3_dap_read_coreregister_u32(swjdp, value, num); @@ -1263,35 +1290,41 @@ int cortex_m3_load_core_reg_u32(struct target_s *target, enum armv7m_regtype typ return ERROR_JTAG_DEVICE_ERROR; } LOG_DEBUG("load from core reg %i value 0x%" PRIx32 "",(int)num,*value); - } - else if (type == ARMV7M_REGISTER_CORE_SP) /* Special purpose core register */ - { - /* read other registers */ + break; + + case ARMV7M_PRIMASK: + case ARMV7M_BASEPRI: + case ARMV7M_FAULTMASK: + case ARMV7M_CONTROL: + /* Cortex-M3 packages these four registers as bitfields + * in one Debug Core register. So say r0 and r2 docs; + * it was removed from r1 docs, but still works. + */ cortexm3_dap_read_coreregister_u32(swjdp, value, 20); switch (num) { - case 19: - *value = buf_get_u32((uint8_t*)value, 0, 8); + case ARMV7M_PRIMASK: + *value = buf_get_u32((uint8_t*)value, 0, 1); break; - case 20: + case ARMV7M_BASEPRI: *value = buf_get_u32((uint8_t*)value, 8, 8); break; - case 21: - *value = buf_get_u32((uint8_t*)value, 16, 8); + case ARMV7M_FAULTMASK: + *value = buf_get_u32((uint8_t*)value, 16, 1); break; - case 22: - *value = buf_get_u32((uint8_t*)value, 24, 8); + case ARMV7M_CONTROL: + *value = buf_get_u32((uint8_t*)value, 24, 2); break; } LOG_DEBUG("load from special reg %i value 0x%" PRIx32 "", (int)num, *value); - } - else - { + break; + + default: return ERROR_INVALID_ARGUMENTS; } @@ -1312,14 +1345,19 @@ int cortex_m3_store_core_reg_u32(struct target_s *target, enum armv7m_regtype ty * in "thumb" mode, or an INVSTATE exception will occur. This is a * hack to deal with the fact that gdb will sometimes "forge" * return addresses, and doesn't set the LSB correctly (i.e., when - * printing expressions containing function calls, it sets LR = 0.) */ - - if (num == 14) + * printing expressions containing function calls, it sets LR = 0.) + * Valid exception return codes have bit 0 set too. + */ + if (num == ARMV7M_R14) value |= 0x01; #endif - if ((type == ARMV7M_REGISTER_CORE_GP) && (num <= ARMV7M_PSP)) - { + /* NOTE: we "know" here that the register identifiers used + * in the v7m header match the Cortex-M3 Debug Core Register + * Selector values for R0..R15, xPSR, MSP, and PSP. + */ + switch (num) { + case 0 ... 18: retval = cortexm3_dap_write_coreregister_u32(swjdp, value, num); if (retval != ERROR_OK) { @@ -1328,38 +1366,43 @@ int cortex_m3_store_core_reg_u32(struct target_s *target, enum armv7m_regtype ty return ERROR_JTAG_DEVICE_ERROR; } LOG_DEBUG("write core reg %i value 0x%" PRIx32 "", (int)num, value); - } - else if (type == ARMV7M_REGISTER_CORE_SP) /* Special purpose core register */ - { - /* write other registers */ - + break; + + case ARMV7M_PRIMASK: + case ARMV7M_BASEPRI: + case ARMV7M_FAULTMASK: + case ARMV7M_CONTROL: + /* Cortex-M3 packages these four registers as bitfields + * in one Debug Core register. So say r0 and r2 docs; + * it was removed from r1 docs, but still works. + */ cortexm3_dap_read_coreregister_u32(swjdp, ®, 20); switch (num) { - case 19: - buf_set_u32((uint8_t*)®, 0, 8, value); + case ARMV7M_PRIMASK: + buf_set_u32((uint8_t*)®, 0, 1, value); break; - case 20: + case ARMV7M_BASEPRI: buf_set_u32((uint8_t*)®, 8, 8, value); break; - case 21: - buf_set_u32((uint8_t*)®, 16, 8, value); + case ARMV7M_FAULTMASK: + buf_set_u32((uint8_t*)®, 16, 1, value); break; - case 22: - buf_set_u32((uint8_t*)®, 24, 8, value); + case ARMV7M_CONTROL: + buf_set_u32((uint8_t*)®, 24, 2, value); break; } cortexm3_dap_write_coreregister_u32(swjdp, reg, 20); LOG_DEBUG("write special reg %i value 0x%" PRIx32 " ", (int)num, value); - } - else - { + break; + + default: return ERROR_INVALID_ARGUMENTS; } @@ -1646,6 +1689,118 @@ int cortex_m3_target_create(struct target_s *target, Jim_Interp *interp) return ERROR_OK; } +/* + * REVISIT Thumb2 disassembly should work for all ARMv7 cores, as well + * as at least ARM-1156T2. The interesting thing about Cortex-M is + * that *only* Thumb2 disassembly matters. There are also some small + * additions to Thumb2 that are specific to ARMv7-M. + */ +static int +handle_cortex_m3_disassemble_command(struct command_context_s *cmd_ctx, + char *cmd, char **args, int argc) +{ + int retval = ERROR_OK; + target_t *target = get_current_target(cmd_ctx); + uint32_t address; + unsigned long count = 1; + arm_instruction_t cur_instruction; + + errno = 0; + switch (argc) { + case 2: + count = strtoul(args[1], NULL, 0); + if (errno) + return ERROR_FAIL; + /* FALL THROUGH */ + case 1: + address = strtoul(args[0], NULL, 0); + if (errno) + return ERROR_FAIL; + break; + default: + command_print(cmd_ctx, + "usage: cortex_m3 disassemble
[]"); + return ERROR_OK; + } + + while (count--) { + retval = thumb2_opcode(target, address, &cur_instruction); + if (retval != ERROR_OK) + return retval; + command_print(cmd_ctx, "%s", cur_instruction.text); + address += cur_instruction.instruction_size; + } + + return ERROR_OK; +} + +static const struct { + char name[10]; + unsigned mask; +} vec_ids[] = { + { "hard_err", VC_HARDERR, }, + { "int_err", VC_INTERR, }, + { "bus_err", VC_BUSERR, }, + { "state_err", VC_STATERR, }, + { "chk_err", VC_CHKERR, }, + { "nocp_err", VC_NOCPERR, }, + { "mm_err", VC_MMERR, }, + { "reset", VC_CORERESET, }, +}; + +static int +handle_cortex_m3_vector_catch_command(struct command_context_s *cmd_ctx, + char *cmd, char **argv, int argc) +{ + target_t *target = get_current_target(cmd_ctx); + armv7m_common_t *armv7m = target->arch_info; + swjdp_common_t *swjdp = &armv7m->swjdp_info; + uint32_t demcr = 0; + int i; + + mem_ap_read_atomic_u32(swjdp, DCB_DEMCR, &demcr); + + if (argc > 0) { + unsigned catch = 0; + + if (argc == 1) { + if (strcmp(argv[0], "all") == 0) { + catch = VC_HARDERR | VC_INTERR | VC_BUSERR + | VC_STATERR | VC_CHKERR | VC_NOCPERR + | VC_MMERR | VC_CORERESET; + goto write; + } else if (strcmp(argv[0], "none") == 0) { + goto write; + } + } + while (argc-- > 0) { + for (i = 0; i < ARRAY_SIZE(vec_ids); i++) { + if (strcmp(argv[argc], vec_ids[i].name) != 0) + continue; + catch |= vec_ids[i].mask; + break; + } + if (i == ARRAY_SIZE(vec_ids)) { + LOG_ERROR("No CM3 vector '%s'", argv[argc]); + return ERROR_INVALID_ARGUMENTS; + } + } +write: + demcr &= ~0xffff; + demcr |= catch; + + /* write, but don't assume it stuck */ + mem_ap_write_u32(swjdp, DCB_DEMCR, demcr); + mem_ap_read_atomic_u32(swjdp, DCB_DEMCR, &demcr); + } + + for (i = 0; i < ARRAY_SIZE(vec_ids); i++) + command_print(cmd_ctx, "%9s: %s", vec_ids[i].name, + (demcr & vec_ids[i].mask) ? "catch" : "ignore"); + + return ERROR_OK; +} + int cortex_m3_register_commands(struct command_context_s *cmd_ctx) { int retval; @@ -1653,8 +1808,18 @@ int cortex_m3_register_commands(struct command_context_s *cmd_ctx) retval = armv7m_register_commands(cmd_ctx); - cortex_m3_cmd = register_command(cmd_ctx, NULL, "cortex_m3", NULL, COMMAND_ANY, "cortex_m3 specific commands"); - register_command(cmd_ctx, cortex_m3_cmd, "maskisr", handle_cortex_m3_mask_interrupts_command, COMMAND_EXEC, "mask cortex_m3 interrupts ['on'|'off']"); + cortex_m3_cmd = register_command(cmd_ctx, NULL, "cortex_m3", + NULL, COMMAND_ANY, "cortex_m3 specific commands"); + + register_command(cmd_ctx, cortex_m3_cmd, "disassemble", + handle_cortex_m3_disassemble_command, COMMAND_EXEC, + "disassemble Thumb2 instructions
[]"); + register_command(cmd_ctx, cortex_m3_cmd, "maskisr", + handle_cortex_m3_mask_interrupts_command, COMMAND_EXEC, + "mask cortex_m3 interrupts ['on'|'off']"); + register_command(cmd_ctx, cortex_m3_cmd, "vector_catch", + handle_cortex_m3_vector_catch_command, COMMAND_EXEC, + "catch hardware vectors ['all'|'none'|]"); return retval; }