X-Git-Url: https://review.openocd.org/gitweb?a=blobdiff_plain;f=src%2Ftarget%2Fcortex_m3.c;h=bdb405039df0590441d3f8674494a62748c4401c;hb=815c3b353307796fb4d86a1880679dacaed00b6e;hp=279d986a6b9b049df9b4f584b5240be6671d059a;hpb=68b97e4b5c40a70b42dc2a970f1b90b9a3e9f13d;p=openocd.git

diff --git a/src/target/cortex_m3.c b/src/target/cortex_m3.c
index 279d986a6b..bdb405039d 100644
--- a/src/target/cortex_m3.c
+++ b/src/target/cortex_m3.c
@@ -137,7 +137,7 @@ int cortex_m3_exec_opcode(target_t *target,u32 opcode, int len /* MODE, r0_inval
 	ahbap_write_system_u32(swjdp, 0x20000000, opcode);
 	ahbap_write_coreregister_u32(swjdp, 0x20000000, 15);
 	cortex_m3_single_step_core(target);
-	armv7m->core_cache->reg_list[15].dirty = 1;
+	armv7m->core_cache->reg_list[15].dirty = armv7m->core_cache->reg_list[15].valid;
 	retvalue = ahbap_write_system_atomic_u32(swjdp, 0x20000000, savedram);		
 	
 	return retvalue;
@@ -320,7 +320,7 @@ int cortex_m3_debug_entry(target_t *target)
 	/* For IT instructions xPSR must be reloaded on resume and clear on debug exec*/
 	if (xPSR & 0xf00)
 	{
-		armv7m->core_cache->reg_list[ARMV7M_xPSR].dirty = 1;
+		armv7m->core_cache->reg_list[ARMV7M_xPSR].dirty = armv7m->core_cache->reg_list[ARMV7M_xPSR].valid;
 		cortex_m3_store_core_reg_u32(target, ARMV7M_REGISTER_CORE_GP, 16, xPSR &~ 0xff);
 	}
 
@@ -348,7 +348,7 @@ int cortex_m3_debug_entry(target_t *target)
 	return ERROR_OK;
 }
 
-enum target_state cortex_m3_poll(target_t *target)
+int cortex_m3_poll(target_t *target)
 {
 	int retval;
 	u32 prev_target_state = target->state;
@@ -363,7 +363,7 @@ enum target_state cortex_m3_poll(target_t *target)
 	if (retval != ERROR_OK)
 	{
 		target->state = TARGET_UNKNOWN;
-		return TARGET_UNKNOWN;
+		return retval;
 	}
 	
 	if (cortex_m3->dcb_dhcsr & S_RESET_ST)
@@ -374,7 +374,7 @@ enum target_state cortex_m3_poll(target_t *target)
 		if (cortex_m3->dcb_dhcsr & S_RESET_ST)
 		{
 			target->state = TARGET_RESET;
-			return target->state;
+			return ERROR_OK;
 		}
 	}
 	
@@ -394,7 +394,7 @@ enum target_state cortex_m3_poll(target_t *target)
 		if ((prev_target_state == TARGET_RUNNING) || (prev_target_state == TARGET_RESET))
 		{
 			if ((retval = cortex_m3_debug_entry(target)) != ERROR_OK)
-				return TARGET_UNKNOWN;
+				return retval;
 			
 			target_call_event_callbacks(target, TARGET_EVENT_HALTED);
 		}
@@ -402,7 +402,7 @@ enum target_state cortex_m3_poll(target_t *target)
 		{
 			DEBUG(" ");
 			if ((retval = cortex_m3_debug_entry(target)) != ERROR_OK)
-				return TARGET_UNKNOWN;
+				return retval;
 
 			target_call_event_callbacks(target, TARGET_EVENT_DEBUG_HALTED);
 		}
@@ -416,7 +416,7 @@ enum target_state cortex_m3_poll(target_t *target)
     /* Read Debug Fault Status Register, added to figure out the lockup when running flashtest.script  */
     ahbap_read_system_atomic_u32(swjdp, NVIC_DFSR, &cortex_m3->nvic_dfsr);
 	DEBUG("dcb_dhcsr 0x%x, nvic_dfsr 0x%x, target->state: %s", cortex_m3->dcb_dhcsr, cortex_m3->nvic_dfsr, target_state_strings[target->state]);	
-	return target->state;
+	return ERROR_OK;
 }
 
 int cortex_m3_halt(target_t *target)
@@ -1149,8 +1149,8 @@ int cortex_m3_load_core_reg_u32(struct target_s *target, enum armv7m_regtype typ
 		ahbap_write_coreregister_u32(swjdp, 0x20000000, 15);
 		cortex_m3_single_step_core(target);
 		ahbap_read_coreregister_u32(swjdp, value, 0);
-		armv7m->core_cache->reg_list[0].dirty = 1;
-		armv7m->core_cache->reg_list[15].dirty = 1;
+		armv7m->core_cache->reg_list[0].dirty = armv7m->core_cache->reg_list[0].valid;
+		armv7m->core_cache->reg_list[15].dirty = armv7m->core_cache->reg_list[15].valid;
 		ahbap_write_system_u32(swjdp, 0x20000000, savedram);
 		swjdp_transaction_endcheck(swjdp);
 		DEBUG("load from special reg %i value 0x%x", SYSm, *value);
@@ -1175,7 +1175,7 @@ int cortex_m3_store_core_reg_u32(struct target_s *target, enum armv7m_regtype ty
 		if (retval != ERROR_OK)
 		{
 			ERROR("JTAG failure %i", retval);
-			armv7m->core_cache->reg_list[num].dirty = 1;
+			armv7m->core_cache->reg_list[num].dirty = armv7m->core_cache->reg_list[num].valid;
 			return ERROR_JTAG_DEVICE_ERROR;
 		}
 		DEBUG("write core reg %i value 0x%x", num, value);
@@ -1195,7 +1195,7 @@ int cortex_m3_store_core_reg_u32(struct target_s *target, enum armv7m_regtype ty
 		ahbap_write_coreregister_u32(swjdp, 0x20000000, 15);
 		cortex_m3_single_step_core(target);
 		ahbap_write_coreregister_u32(swjdp, tempr0, 0);
-		armv7m->core_cache->reg_list[15].dirty = 1;
+		armv7m->core_cache->reg_list[15].dirty = armv7m->core_cache->reg_list[15].valid;
 		ahbap_write_system_u32(swjdp, 0x20000000, savedram);
 		swjdp_transaction_endcheck(swjdp);
 		DEBUG("write special reg %i value 0x%x ", SYSm, value);