X-Git-Url: https://review.openocd.org/gitweb?a=blobdiff_plain;f=src%2Ftarget%2Fcortex_m3.c;h=5816981ccfeeb9e6ecd72be054844b4f0a9b7140;hb=d03e5d0ada1fed216bf313cb4a2d08482ca5e74c;hp=aba15e7f547033160af1509e70a706b5d99b039c;hpb=d47e1b8f362379d8a2307f49e2b42115a3f40524;p=openocd.git diff --git a/src/target/cortex_m3.c b/src/target/cortex_m3.c index aba15e7f54..5816981ccf 100644 --- a/src/target/cortex_m3.c +++ b/src/target/cortex_m3.c @@ -5,6 +5,9 @@ * Copyright (C) 2006 by Magnus Lundin * * lundin@mlu.mine.nu * * * + * Copyright (C) 2008 by Spencer Oliver * + * spen@spen-soft.co.uk * + * * * This program is free software; you can redistribute it and/or modify * * it under the terms of the GNU General Public License as published by * * the Free Software Foundation; either version 2 of the License, or * @@ -41,18 +44,23 @@ /* cli handling */ int cortex_m3_register_commands(struct command_context_s *cmd_ctx); +int handle_cortex_m3_mask_interrupts_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc); /* forward declarations */ -void cortex_m3_unset_all_breakpoints_and_watchpoints(struct target_s *target); void cortex_m3_enable_breakpoints(struct target_s *target); void cortex_m3_enable_watchpoints(struct target_s *target); -void cortex_m3_disable_bkpts_and_wpts(struct target_s *target); -int cortex_m3_target_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, struct target_s *target); +int cortex_m3_target_create(struct target_s *target, Jim_Interp *interp); int cortex_m3_init_target(struct command_context_s *cmd_ctx, struct target_s *target); -int cortex_m3_quit(); +int cortex_m3_quit(void); int cortex_m3_load_core_reg_u32(target_t *target, enum armv7m_regtype type, u32 num, u32 *value); int cortex_m3_store_core_reg_u32(target_t *target, enum armv7m_regtype type, u32 num, u32 value); int cortex_m3_target_request_data(target_t *target, u32 size, u8 *buffer); +int cortex_m3_examine(struct target_s *target); + +#ifdef ARMV7_GDB_HACKS +extern u8 armv7m_gdb_dummy_cpsr_value[]; +extern reg_t armv7m_gdb_dummy_cpsr_reg; +#endif target_type_t cortexm3_target = { @@ -70,7 +78,6 @@ target_type_t cortexm3_target = .assert_reset = cortex_m3_assert_reset, .deassert_reset = cortex_m3_deassert_reset, .soft_reset_halt = cortex_m3_soft_reset_halt, - .prepare_reset_halt = cortex_m3_prepare_reset_halt, .get_gdb_reg_list = armv7m_get_gdb_reg_list, @@ -78,6 +85,7 @@ target_type_t cortexm3_target = .write_memory = cortex_m3_write_memory, .bulk_write_memory = cortex_m3_bulk_write_memory, .checksum_memory = armv7m_checksum_memory, + .blank_check_memory = armv7m_blank_check_memory, .run_algorithm = armv7m_run_algorithm, @@ -87,25 +95,44 @@ target_type_t cortexm3_target = .remove_watchpoint = cortex_m3_remove_watchpoint, .register_commands = cortex_m3_register_commands, - .target_command = cortex_m3_target_command, + .target_create = cortex_m3_target_create, .init_target = cortex_m3_init_target, + .examine = cortex_m3_examine, .quit = cortex_m3_quit }; +int cortex_m3_write_debug_halt_mask(target_t *target, u32 mask_on, u32 mask_off) +{ + /* get pointers to arch-specific information */ + armv7m_common_t *armv7m = target->arch_info; + cortex_m3_common_t *cortex_m3 = armv7m->arch_info; + swjdp_common_t *swjdp = &cortex_m3->swjdp_info; + + /* mask off status bits */ + cortex_m3->dcb_dhcsr &= ~((0xFFFF << 16) | mask_off); + /* create new register mask */ + cortex_m3->dcb_dhcsr |= DBGKEY | C_DEBUGEN | mask_on; + + return ahbap_write_system_atomic_u32(swjdp, DCB_DHCSR, cortex_m3->dcb_dhcsr); +} + int cortex_m3_clear_halt(target_t *target) { /* get pointers to arch-specific information */ armv7m_common_t *armv7m = target->arch_info; cortex_m3_common_t *cortex_m3 = armv7m->arch_info; swjdp_common_t *swjdp = &cortex_m3->swjdp_info; - - /* Read Debug Fault Status Register */ - ahbap_read_system_atomic_u32(swjdp, NVIC_DFSR, &cortex_m3->nvic_dfsr); - /* Write Debug Fault Status Register to enable processing to resume ?? Try with and without this !! */ - ahbap_write_system_atomic_u32(swjdp, NVIC_DFSR, cortex_m3->nvic_dfsr); - LOG_DEBUG(" NVIC_DFSR 0x%x", cortex_m3->nvic_dfsr); - - return ERROR_OK; + + /* clear step if any */ + cortex_m3_write_debug_halt_mask(target, C_HALT, C_STEP); + + /* Read Debug Fault Status Register */ + ahbap_read_system_atomic_u32(swjdp, NVIC_DFSR, &cortex_m3->nvic_dfsr); + /* Write Debug Fault Status Register to enable processing to resume ?? Try with and without this !! */ + ahbap_write_system_atomic_u32(swjdp, NVIC_DFSR, cortex_m3->nvic_dfsr); + LOG_DEBUG(" NVIC_DFSR 0x%x", cortex_m3->nvic_dfsr); + + return ERROR_OK; } int cortex_m3_single_step_core(target_t *target) @@ -114,12 +141,19 @@ int cortex_m3_single_step_core(target_t *target) armv7m_common_t *armv7m = target->arch_info; cortex_m3_common_t *cortex_m3 = armv7m->arch_info; swjdp_common_t *swjdp = &cortex_m3->swjdp_info; - + u32 dhcsr_save; + + /* backup dhcsr reg */ + dhcsr_save = cortex_m3->dcb_dhcsr; + + /* mask interrupts if not done already */ if (!(cortex_m3->dcb_dhcsr & C_MASKINTS)) - ahbap_write_system_atomic_u32(swjdp, DCB_DHCSR, DBGKEY | C_MASKINTS | C_HALT | C_DEBUGEN ); - ahbap_write_system_atomic_u32(swjdp, DCB_DHCSR, DBGKEY | C_MASKINTS | C_STEP | C_DEBUGEN ); - cortex_m3->dcb_dhcsr |= C_MASKINTS; + ahbap_write_system_atomic_u32(swjdp, DCB_DHCSR, DBGKEY | C_MASKINTS | C_HALT | C_DEBUGEN); + ahbap_write_system_atomic_u32(swjdp, DCB_DHCSR, DBGKEY | C_MASKINTS | C_STEP | C_DEBUGEN); LOG_DEBUG(" "); + + /* restore dhcsr reg */ + cortex_m3->dcb_dhcsr = dhcsr_save; cortex_m3_clear_halt(target); return ERROR_OK; @@ -139,7 +173,7 @@ int cortex_m3_exec_opcode(target_t *target,u32 opcode, int len /* MODE, r0_inval ahbap_write_coreregister_u32(swjdp, 0x20000000, 15); cortex_m3_single_step_core(target); armv7m->core_cache->reg_list[15].dirty = armv7m->core_cache->reg_list[15].valid; - retvalue = ahbap_write_system_atomic_u32(swjdp, 0x20000000, savedram); + retvalue = ahbap_write_system_atomic_u32(swjdp, 0x20000000, savedram); return retvalue; } @@ -173,16 +207,21 @@ int cortex_m3_endreset_event(target_t *target) ahbap_read_system_atomic_u32(swjdp, DCB_DEMCR, &dcb_demcr); LOG_DEBUG("DCB_DEMCR = 0x%8.8x",dcb_demcr); - ahbap_write_system_u32(swjdp, DCB_DCRDR, 0 ); + /* this regsiter is used for emulated dcc channel */ + ahbap_write_system_u32(swjdp, DCB_DCRDR, 0); /* Enable debug requests */ ahbap_read_system_atomic_u32(swjdp, DCB_DHCSR, &cortex_m3->dcb_dhcsr); if (!(cortex_m3->dcb_dhcsr & C_DEBUGEN)) - ahbap_write_system_u32(swjdp, DCB_DHCSR, DBGKEY | C_DEBUGEN ); + ahbap_write_system_u32(swjdp, DCB_DHCSR, DBGKEY | C_DEBUGEN); + + /* clear any interrupt masking */ + cortex_m3_write_debug_halt_mask(target, 0, C_MASKINTS); + /* Enable trace and dwt */ - ahbap_write_system_u32(swjdp, DCB_DEMCR, TRCENA | VC_HARDERR | VC_BUSERR ); + ahbap_write_system_u32(swjdp, DCB_DEMCR, TRCENA | VC_HARDERR | VC_BUSERR); /* Monitor bus faults */ - ahbap_write_system_u32(swjdp, NVIC_SHCSR, SHCSR_BUSFAULTENA ); + ahbap_write_system_u32(swjdp, NVIC_SHCSR, SHCSR_BUSFAULTENA); /* Enable FPB */ target_write_u32(target, FP_CTRL, 3); @@ -202,11 +241,6 @@ int cortex_m3_endreset_event(target_t *target) } swjdp_transaction_endcheck(swjdp); - /* Make sure working_areas are all free */ - target_free_all_working_areas(target); - - /* We are in process context */ - armv7m_use_context(target, ARMV7M_PROCESS_CONTEXT); armv7m_invalidate_core_regs(target); return ERROR_OK; } @@ -284,8 +318,8 @@ int cortex_m3_examine_exception_reason(target_t *target) break; } swjdp_transaction_endcheck(swjdp); - LOG_DEBUG("%s SHCSR 0x%x, SR 0x%x, CFSR 0x%x, AR 0x%x", armv7m_exception_string(armv7m->exception_number), \ - shcsr, except_sr, cfsr, except_ar); + LOG_DEBUG("%s SHCSR 0x%x, SR 0x%x, CFSR 0x%x, AR 0x%x", armv7m_exception_string(armv7m->exception_number), \ + shcsr, except_sr, cfsr, except_ar); return ERROR_OK; } @@ -319,7 +353,15 @@ int cortex_m3_debug_entry(target_t *target) } xPSR = buf_get_u32(armv7m->core_cache->reg_list[ARMV7M_xPSR].value, 0, 32); - + +#ifdef ARMV7_GDB_HACKS + /* copy real xpsr reg for gdb, setting thumb bit */ + buf_set_u32(armv7m_gdb_dummy_cpsr_value, 0, 32, xPSR); + buf_set_u32(armv7m_gdb_dummy_cpsr_value, 5, 1, 1); + armv7m_gdb_dummy_cpsr_reg.valid = armv7m->core_cache->reg_list[ARMV7M_xPSR].valid; + armv7m_gdb_dummy_cpsr_reg.dirty = armv7m->core_cache->reg_list[ARMV7M_xPSR].dirty; +#endif + /* For IT instructions xPSR must be reloaded on resume and clear on debug exec */ if (xPSR & 0xf00) { @@ -327,23 +369,34 @@ int cortex_m3_debug_entry(target_t *target) cortex_m3_store_core_reg_u32(target, ARMV7M_REGISTER_CORE_GP, 16, xPSR &~ 0xff); } - /* Now we can load SP core registers */ + /* Now we can load SP core registers */ for (i = ARMV7M_PRIMASK; i < ARMV7NUMCOREREGS; i++) { if (!armv7m->core_cache->reg_list[i].valid) - armv7m->read_core_reg(target, i); + armv7m->read_core_reg(target, i); } /* Are we in an exception handler */ - armv7m->core_mode = (xPSR & 0x1FF) ? ARMV7M_MODE_HANDLER : ARMV7M_MODE_THREAD; - armv7m->exception_number = xPSR & 0x1FF; + if (xPSR & 0x1FF) + { + armv7m->core_mode = ARMV7M_MODE_HANDLER; + armv7m->exception_number = (xPSR & 0x1FF); + } + else + { + armv7m->core_mode = buf_get_u32(armv7m->core_cache->reg_list[ARMV7M_CONTROL].value, 0, 1); + armv7m->exception_number = 0; + } + if (armv7m->exception_number) { cortex_m3_examine_exception_reason(target); } - LOG_DEBUG("entered debug state in core mode: %s at PC 0x%x, target->state: %s", armv7m_mode_strings[armv7m->core_mode], \ - *(u32*)(armv7m->core_cache->reg_list[15].value), target_state_strings[target->state]); + LOG_DEBUG("entered debug state in core mode: %s at PC 0x%x, target->state: %s", + armv7m_mode_strings[armv7m->core_mode], + *(u32*)(armv7m->core_cache->reg_list[15].value), + Jim_Nvp_value2name_simple( nvp_target_state, target->state )->name); if (armv7m->post_debug_entry) armv7m->post_debug_entry(target); @@ -354,7 +407,7 @@ int cortex_m3_debug_entry(target_t *target) int cortex_m3_poll(target_t *target) { int retval; - u32 prev_target_state = target->state; + enum target_state prev_target_state = target->state; /* get pointers to arch-specific information */ armv7m_common_t *armv7m = target->arch_info; @@ -416,24 +469,23 @@ int cortex_m3_poll(target_t *target) target->state = TARGET_SLEEP; */ - /* Read Debug Fault Status Register, added to figure out the lockup when running flashtest.script */ - ahbap_read_system_atomic_u32(swjdp, NVIC_DFSR, &cortex_m3->nvic_dfsr); - LOG_DEBUG("dcb_dhcsr 0x%x, nvic_dfsr 0x%x, target->state: %s", cortex_m3->dcb_dhcsr, cortex_m3->nvic_dfsr, target_state_strings[target->state]); +#if 0 + /* Read Debug Fault Status Register, added to figure out the lockup when running flashtest.script */ + ahbap_read_system_atomic_u32(swjdp, NVIC_DFSR, &cortex_m3->nvic_dfsr); + LOG_DEBUG("dcb_dhcsr 0x%x, nvic_dfsr 0x%x, target->state: %s", cortex_m3->dcb_dhcsr, cortex_m3->nvic_dfsr, Jim_Nvp_value2name_simple( nvp_target_state, target->state )->name ); +#endif + return ERROR_OK; } int cortex_m3_halt(target_t *target) { - /* get pointers to arch-specific information */ - armv7m_common_t *armv7m = target->arch_info; - cortex_m3_common_t *cortex_m3 = armv7m->arch_info; - swjdp_common_t *swjdp = &cortex_m3->swjdp_info; - - LOG_DEBUG("target->state: %s", target_state_strings[target->state]); + LOG_DEBUG("target->state: %s", + Jim_Nvp_value2name_simple(nvp_target_state, target->state )->name); if (target->state == TARGET_HALTED) { - LOG_WARNING("target was already halted"); + LOG_DEBUG("target was already halted"); return ERROR_OK; } @@ -461,7 +513,7 @@ int cortex_m3_halt(target_t *target) } /* Write to Debug Halting Control and Status Register */ - ahbap_write_system_atomic_u32(swjdp, DCB_DHCSR, DBGKEY | C_DEBUGEN | C_HALT ); + cortex_m3_write_debug_halt_mask(target, C_HALT, 0); target->debug_reason = DBG_REASON_DBGRQ; @@ -476,19 +528,12 @@ int cortex_m3_soft_reset_halt(struct target_s *target) swjdp_common_t *swjdp = &cortex_m3->swjdp_info; u32 dcb_dhcsr = 0; int retval, timeout = 0; - - /* Check that we are using process_context, or change and print warning */ - if (armv7m_get_context(target) != ARMV7M_PROCESS_CONTEXT) - { - LOG_DEBUG("Changing to process contex registers"); - armv7m_use_context(target, ARMV7M_PROCESS_CONTEXT); - } /* Enter debug state on reset, cf. end_reset_event() */ - ahbap_write_system_u32(swjdp, DCB_DEMCR, TRCENA | VC_HARDERR | VC_BUSERR | VC_CORERESET ); + ahbap_write_system_u32(swjdp, DCB_DEMCR, TRCENA | VC_HARDERR | VC_BUSERR | VC_CORERESET); /* Request a reset */ - ahbap_write_system_atomic_u32(swjdp, NVIC_AIRCR, AIRCR_VECTKEY | AIRCR_VECTRESET ); + ahbap_write_system_atomic_u32(swjdp, NVIC_AIRCR, AIRCR_VECTKEY | AIRCR_VECTRESET); target->state = TARGET_RESET; /* registers are now invalid */ @@ -499,7 +544,7 @@ int cortex_m3_soft_reset_halt(struct target_s *target) retval = ahbap_read_system_atomic_u32(swjdp, DCB_DHCSR, &dcb_dhcsr); if (retval == ERROR_OK) { - ahbap_read_system_atomic_u32(swjdp, NVIC_DFSR, &cortex_m3->nvic_dfsr); + ahbap_read_system_atomic_u32(swjdp, NVIC_DFSR, &cortex_m3->nvic_dfsr); if ((dcb_dhcsr & S_HALT) && (cortex_m3->nvic_dfsr & DFSR_VCATCH)) { LOG_DEBUG("system reset-halted, dcb_dhcsr 0x%x, nvic_dfsr 0x%x", dcb_dhcsr, cortex_m3->nvic_dfsr); @@ -510,42 +555,18 @@ int cortex_m3_soft_reset_halt(struct target_s *target) LOG_DEBUG("waiting for system reset-halt, dcb_dhcsr 0x%x, %i ms", dcb_dhcsr, timeout); } timeout++; - usleep(1000); + alive_sleep(1); } return ERROR_OK; } -int cortex_m3_prepare_reset_halt(struct target_s *target) -{ - armv7m_common_t *armv7m = target->arch_info; - cortex_m3_common_t *cortex_m3 = armv7m->arch_info; - swjdp_common_t *swjdp = &cortex_m3->swjdp_info; - u32 dcb_demcr, dcb_dhcsr; - - /* Enable debug requests */ - ahbap_read_system_atomic_u32(swjdp, DCB_DHCSR, &cortex_m3->dcb_dhcsr); - if (!(cortex_m3->dcb_dhcsr & C_DEBUGEN)) - ahbap_write_system_u32(swjdp, DCB_DHCSR, DBGKEY | C_DEBUGEN ); - - /* Enter debug state on reset, cf. end_reset_event() */ - ahbap_write_system_atomic_u32(swjdp, DCB_DEMCR, TRCENA | VC_HARDERR | VC_BUSERR | VC_CORERESET ); - - ahbap_read_system_atomic_u32(swjdp, DCB_DHCSR, &dcb_dhcsr); - ahbap_read_system_atomic_u32(swjdp, DCB_DEMCR, &dcb_demcr); - LOG_DEBUG("dcb_dhcsr 0x%x, dcb_demcr 0x%x, ", dcb_dhcsr, dcb_demcr); - - return ERROR_OK; -} - int cortex_m3_resume(struct target_s *target, int current, u32 address, int handle_breakpoints, int debug_execution) { /* get pointers to arch-specific information */ armv7m_common_t *armv7m = target->arch_info; - cortex_m3_common_t *cortex_m3 = armv7m->arch_info; - swjdp_common_t *swjdp = &cortex_m3->swjdp_info; breakpoint_t *breakpoint = NULL; - u32 dcb_dhcsr, resume_pc; + u32 resume_pc; if (target->state != TARGET_HALTED) { @@ -555,39 +576,26 @@ int cortex_m3_resume(struct target_s *target, int current, u32 address, int hand if (!debug_execution) { - /* Check that we are using process_context, or change and print warning */ - if (armv7m_get_context(target) != ARMV7M_PROCESS_CONTEXT) - { - LOG_DEBUG("Incorrect context in resume"); - armv7m_use_context(target, ARMV7M_PROCESS_CONTEXT); - } - target_free_all_working_areas(target); cortex_m3_enable_breakpoints(target); cortex_m3_enable_watchpoints(target); - - /* TODOLATER Interrupt handling/disable for debug execution, cache ... ... */ } - dcb_dhcsr = DBGKEY | C_DEBUGEN; if (debug_execution) { - /* Check that we are using debug_context, or change and print warning */ - if (armv7m_get_context(target) != ARMV7M_DEBUG_CONTEXT) - { - LOG_DEBUG("Incorrect context in debug_exec resume"); - armv7m_use_context(target, ARMV7M_DEBUG_CONTEXT); - } /* Disable interrupts */ - /* - We disable interrupts in the PRIMASK register instead of masking with C_MASKINTS, - This is probably the same inssue as Cortex-M3 Errata 377493: - C_MASKINTS in parallel with disabled interrupts can cause local faults to not be taken. - */ + /* We disable interrupts in the PRIMASK register instead of masking with C_MASKINTS, + * This is probably the same issue as Cortex-M3 Errata 377493: + * C_MASKINTS in parallel with disabled interrupts can cause local faults to not be taken. */ buf_set_u32(armv7m->core_cache->reg_list[ARMV7M_PRIMASK].value, 0, 32, 1); + armv7m->core_cache->reg_list[ARMV7M_PRIMASK].dirty = 1; + armv7m->core_cache->reg_list[ARMV7M_PRIMASK].valid = 1; + /* Make sure we are in Thumb mode */ buf_set_u32(armv7m->core_cache->reg_list[ARMV7M_xPSR].value, 0, 32, buf_get_u32(armv7m->core_cache->reg_list[ARMV7M_xPSR].value, 0, 32) | (1<<24)); + armv7m->core_cache->reg_list[ARMV7M_xPSR].dirty = 1; + armv7m->core_cache->reg_list[ARMV7M_xPSR].valid = 1; } /* current = 1: continue on current pc, otherwise continue at
*/ @@ -608,19 +616,16 @@ int cortex_m3_resume(struct target_s *target, int current, u32 address, int hand /* Single step past breakpoint at current address */ if ((breakpoint = breakpoint_find(target, resume_pc))) { - LOG_DEBUG("unset breakpoint at 0x%8.8x", breakpoint->address); - cortex_m3_unset_breakpoint(target, breakpoint); - cortex_m3_single_step_core(target); - cortex_m3_set_breakpoint(target, breakpoint); + LOG_DEBUG("unset breakpoint at 0x%8.8x", breakpoint->address); + cortex_m3_unset_breakpoint(target, breakpoint); + cortex_m3_single_step_core(target); + cortex_m3_set_breakpoint(target, breakpoint); } } - - /* Set/Clear C_MASKINTS in a separate operation */ - if ((cortex_m3->dcb_dhcsr & C_MASKINTS) != (dcb_dhcsr & C_MASKINTS)) - ahbap_write_system_atomic_u32(swjdp, DCB_DHCSR, dcb_dhcsr | C_HALT ); /* Restart core */ - ahbap_write_system_atomic_u32(swjdp, DCB_DHCSR, dcb_dhcsr ); + cortex_m3_write_debug_halt_mask(target, 0, C_HALT); + target->debug_reason = DBG_REASON_NOTHALTED; /* registers are now invalid */ @@ -629,13 +634,13 @@ int cortex_m3_resume(struct target_s *target, int current, u32 address, int hand { target->state = TARGET_RUNNING; target_call_event_callbacks(target, TARGET_EVENT_RESUMED); - LOG_DEBUG("target resumed at 0x%x",resume_pc); + LOG_DEBUG("target resumed at 0x%x", resume_pc); } else { target->state = TARGET_DEBUG_RUNNING; target_call_event_callbacks(target, TARGET_EVENT_DEBUG_RESUMED); - LOG_DEBUG("target debug resumed at 0x%x",resume_pc); + LOG_DEBUG("target debug resumed at 0x%x", resume_pc); } return ERROR_OK; @@ -655,13 +660,6 @@ int cortex_m3_step(struct target_s *target, int current, u32 address, int handle LOG_WARNING("target not halted"); return ERROR_TARGET_NOT_HALTED; } - - /* Check that we are using process_context, or change and print warning */ - if (armv7m_get_context(target) != ARMV7M_PROCESS_CONTEXT) - { - LOG_WARNING("Incorrect context in step, must be process"); - armv7m_use_context(target, ARMV7M_PROCESS_CONTEXT); - } /* current = 1: continue on current pc, otherwise continue at
*/ if (!current) @@ -677,15 +675,13 @@ int cortex_m3_step(struct target_s *target, int current, u32 address, int handle armv7m_restore_context(target); target_call_event_callbacks(target, TARGET_EVENT_RESUMED); - - if (cortex_m3->dcb_dhcsr & C_MASKINTS) - ahbap_write_system_atomic_u32(swjdp, DCB_DHCSR, DBGKEY | C_HALT | C_DEBUGEN ); - ahbap_write_system_atomic_u32(swjdp, DCB_DHCSR, DBGKEY| C_STEP | C_DEBUGEN); + + /* set step and clear halt */ + cortex_m3_write_debug_halt_mask(target, C_STEP, C_HALT); ahbap_read_system_atomic_u32(swjdp, DCB_DHCSR, &cortex_m3->dcb_dhcsr); - /* If we run in process context then registers are now invalid */ - if (armv7m_get_context(target) == ARMV7M_PROCESS_CONTEXT) - armv7m_invalidate_core_regs(target); + /* registers are now invalid */ + armv7m_invalidate_core_regs(target); if (breakpoint) cortex_m3_set_breakpoint(target, breakpoint); @@ -701,86 +697,119 @@ int cortex_m3_step(struct target_s *target, int current, u32 address, int handle int cortex_m3_assert_reset(target_t *target) { - int retval; armv7m_common_t *armv7m = target->arch_info; cortex_m3_common_t *cortex_m3 = armv7m->arch_info; swjdp_common_t *swjdp = &cortex_m3->swjdp_info; + int assert_srst = 1; - LOG_DEBUG("target->state: %s", target_state_strings[target->state]); + LOG_DEBUG("target->state: %s", + Jim_Nvp_value2name_simple( nvp_target_state, target->state )->name ); + if (!(jtag_reset_config & RESET_HAS_SRST)) + { + LOG_ERROR("Can't assert SRST"); + return ERROR_FAIL; + } + + /* Enable debug requests */ + ahbap_read_system_atomic_u32(swjdp, DCB_DHCSR, &cortex_m3->dcb_dhcsr); + if (!(cortex_m3->dcb_dhcsr & C_DEBUGEN)) + ahbap_write_system_u32(swjdp, DCB_DHCSR, DBGKEY | C_DEBUGEN); + ahbap_write_system_u32(swjdp, DCB_DCRDR, 0 ); - if (target->reset_mode == RESET_RUN) + if (!target->reset_halt) { /* Set/Clear C_MASKINTS in a separate operation */ if (cortex_m3->dcb_dhcsr & C_MASKINTS) - ahbap_write_system_atomic_u32(swjdp, DCB_DHCSR, DBGKEY | C_DEBUGEN | C_HALT ); - + ahbap_write_system_atomic_u32(swjdp, DCB_DHCSR, DBGKEY | C_DEBUGEN | C_HALT); + cortex_m3_clear_halt(target); /* Enter debug state on reset, cf. end_reset_event() */ - ahbap_write_system_u32(swjdp, DCB_DHCSR, DBGKEY | C_DEBUGEN ); ahbap_write_system_u32(swjdp, DCB_DEMCR, TRCENA | VC_HARDERR | VC_BUSERR); } + else + { + /* Enter debug state on reset, cf. end_reset_event() */ + ahbap_write_system_atomic_u32(swjdp, DCB_DEMCR, TRCENA | VC_HARDERR | VC_BUSERR | VC_CORERESET); + } - if (target->state == TARGET_HALTED || target->state == TARGET_UNKNOWN) + /* following hack is to handle luminary reset + * when srst is asserted the luminary device seesm to also clear the debug registers + * which does not match the armv7 debug TRM */ + + if (strcmp(cortex_m3->variant, "lm3s") == 0) { - /* assert SRST and TRST */ - /* system would get ouf sync if we didn't reset test-logic, too */ - if ((retval = jtag_add_reset(1, 1)) != ERROR_OK) + /* get revision of lm3s target, only early silicon has this issue + * Fury Rev B, DustDevil Rev B, Tempest all ok */ + + u32 did0; + + if (target_read_u32(target, 0x400fe000, &did0) == ERROR_OK) { - if (retval == ERROR_JTAG_RESET_CANT_SRST) + switch ((did0 >> 16) & 0xff) { - return retval; - } - else - { - LOG_ERROR("unknown error"); - exit(-1); + case 0: + /* all Sandstorm suffer issue */ + assert_srst = 0; + break; + + case 1: + case 3: + /* only Fury/DustDevil rev A suffer reset problems */ + if (((did0 >> 8) & 0xff) == 0) + assert_srst = 0; + break; } } - jtag_add_sleep(5000); - if ((retval = jtag_add_reset(0, 1)) != ERROR_OK) + } + + if (assert_srst) + { + /* default to asserting srst */ + if (jtag_reset_config & RESET_SRST_PULLS_TRST) { - if (retval == ERROR_JTAG_RESET_WOULD_ASSERT_TRST) - { - retval = jtag_add_reset(1, 1); - } + jtag_add_reset(1, 1); + } + else + { + jtag_add_reset(0, 1); } } else { - if ((retval = jtag_add_reset(0, 1)) != ERROR_OK) + /* this causes the luminary device to reset using the watchdog */ + ahbap_write_system_atomic_u32(swjdp, NVIC_AIRCR, AIRCR_VECTKEY | AIRCR_SYSRESETREQ); + LOG_DEBUG("Using Luminary Reset: SYSRESETREQ"); + { - if (retval == ERROR_JTAG_RESET_WOULD_ASSERT_TRST) - { - retval = jtag_add_reset(1, 1); - } - - if (retval == ERROR_JTAG_RESET_CANT_SRST) - { - return retval; - } - else if (retval != ERROR_OK) - { - LOG_ERROR("unknown error"); - exit(-1); - } + /* I do not know why this is necessary, but it fixes strange effects + * (step/resume cause a NMI after reset) on LM3S6918 -- Michael Schwingen */ + u32 tmp; + ahbap_read_system_atomic_u32(swjdp, NVIC_AIRCR, &tmp); } } target->state = TARGET_RESET; jtag_add_sleep(50000); - armv7m_use_context(target, ARMV7M_PROCESS_CONTEXT); armv7m_invalidate_core_regs(target); + if (target->reset_halt) + { + int retval; + if ((retval = target_halt(target))!=ERROR_OK) + return retval; + } + return ERROR_OK; } int cortex_m3_deassert_reset(target_t *target) { - LOG_DEBUG("target->state: %s", target_state_strings[target->state]); + LOG_DEBUG("target->state: %s", + Jim_Nvp_value2name_simple(nvp_target_state, target->state )->name); /* deassert reset lines */ jtag_add_reset(0, 0); @@ -788,11 +817,6 @@ int cortex_m3_deassert_reset(target_t *target) return ERROR_OK; } -void cortex_m3_unset_all_breakpoints_and_watchpoints(struct target_s *target) -{ - -} - void cortex_m3_enable_breakpoints(struct target_s *target) { breakpoint_t *breakpoint = target->breakpoints; @@ -808,6 +832,7 @@ void cortex_m3_enable_breakpoints(struct target_s *target) int cortex_m3_set_breakpoint(struct target_s *target, breakpoint_t *breakpoint) { + int retval; int fp_num=0; u32 hilo; @@ -822,7 +847,7 @@ int cortex_m3_set_breakpoint(struct target_s *target, breakpoint_t *breakpoint) LOG_WARNING("breakpoint already set"); return ERROR_OK; } - + if (cortex_m3->auto_bp_type) { breakpoint->type = (breakpoint->address < 0x20000000) ? BKPT_HARD : BKPT_SOFT; @@ -849,8 +874,14 @@ int cortex_m3_set_breakpoint(struct target_s *target, breakpoint_t *breakpoint) { u8 code[4]; buf_set_u32(code, 0, 32, ARMV7M_T_BKPT(0x11)); - target->type->read_memory(target, breakpoint->address & 0xFFFFFFFE, breakpoint->length, 1, breakpoint->orig_instr); - target->type->write_memory(target, breakpoint->address & 0xFFFFFFFE, breakpoint->length, 1, code); + if((retval = target->type->read_memory(target, breakpoint->address & 0xFFFFFFFE, breakpoint->length, 1, breakpoint->orig_instr)) != ERROR_OK) + { + return retval; + } + if((retval = target->type->write_memory(target, breakpoint->address & 0xFFFFFFFE, breakpoint->length, 1, code)) != ERROR_OK) + { + return retval; + } breakpoint->set = 0x11; /* Any nice value but 0 */ } @@ -859,6 +890,7 @@ int cortex_m3_set_breakpoint(struct target_s *target, breakpoint_t *breakpoint) int cortex_m3_unset_breakpoint(struct target_s *target, breakpoint_t *breakpoint) { + int retval; /* get pointers to arch-specific information */ armv7m_common_t *armv7m = target->arch_info; cortex_m3_common_t *cortex_m3 = armv7m->arch_info; @@ -887,11 +919,17 @@ int cortex_m3_unset_breakpoint(struct target_s *target, breakpoint_t *breakpoint /* restore original instruction (kept in target endianness) */ if (breakpoint->length == 4) { - target->type->write_memory(target, breakpoint->address & 0xFFFFFFFE, 4, 1, breakpoint->orig_instr); + if((retval = target->type->write_memory(target, breakpoint->address & 0xFFFFFFFE, 4, 1, breakpoint->orig_instr)) != ERROR_OK) + { + return retval; + } } else { - target->type->write_memory(target, breakpoint->address & 0xFFFFFFFE, 2, 1, breakpoint->orig_instr); + if((retval = target->type->write_memory(target, breakpoint->address & 0xFFFFFFFE, 2, 1, breakpoint->orig_instr)) != ERROR_OK) + { + return retval; + } } } breakpoint->set = 0; @@ -904,10 +942,18 @@ int cortex_m3_add_breakpoint(struct target_s *target, breakpoint_t *breakpoint) /* get pointers to arch-specific information */ armv7m_common_t *armv7m = target->arch_info; cortex_m3_common_t *cortex_m3 = armv7m->arch_info; - + if (cortex_m3->auto_bp_type) { breakpoint->type = (breakpoint->address < 0x20000000) ? BKPT_HARD : BKPT_SOFT; +#ifdef ARMV7_GDB_HACKS + if (breakpoint->length != 2) { + /* XXX Hack: Replace all breakpoints with length != 2 with + * a hardware breakpoint. */ + breakpoint->type = BKPT_HARD; + breakpoint->length = 2; + } +#endif } if ((breakpoint->type == BKPT_HARD) && (breakpoint->address >= 0x20000000)) @@ -1137,22 +1183,28 @@ int cortex_m3_load_core_reg_u32(struct target_s *target, enum armv7m_regtype typ else if (type == ARMV7M_REGISTER_CORE_SP) /* Special purpose core register */ { /* read other registers */ - u32 savedram; - u32 SYSm; - u32 instr; - SYSm = num & 0x1F; + ahbap_read_coreregister_u32(swjdp, value, 20); + + switch (num) + { + case 19: + *value = buf_get_u32((u8*)value, 0, 8); + break; + + case 20: + *value = buf_get_u32((u8*)value, 8, 8); + break; + + case 21: + *value = buf_get_u32((u8*)value, 16, 8); + break; + + case 22: + *value = buf_get_u32((u8*)value, 24, 8); + break; + } - ahbap_read_system_u32(swjdp, 0x20000000, &savedram); - instr = ARMV7M_T_MRS(0, SYSm); - ahbap_write_system_u32(swjdp, 0x20000000, ARMV7M_T_MRS(0, SYSm)); - ahbap_write_coreregister_u32(swjdp, 0x20000000, 15); - cortex_m3_single_step_core(target); - ahbap_read_coreregister_u32(swjdp, value, 0); - armv7m->core_cache->reg_list[0].dirty = armv7m->core_cache->reg_list[0].valid; - armv7m->core_cache->reg_list[15].dirty = armv7m->core_cache->reg_list[15].valid; - ahbap_write_system_u32(swjdp, 0x20000000, savedram); - swjdp_transaction_endcheck(swjdp); - LOG_DEBUG("load from special reg %i value 0x%x", SYSm, *value); + LOG_DEBUG("load from special reg %i value 0x%x", num, *value); } else { @@ -1165,12 +1217,24 @@ int cortex_m3_load_core_reg_u32(struct target_s *target, enum armv7m_regtype typ int cortex_m3_store_core_reg_u32(struct target_s *target, enum armv7m_regtype type, u32 num, u32 value) { int retval; + u32 reg; /* get pointers to arch-specific information */ armv7m_common_t *armv7m = target->arch_info; cortex_m3_common_t *cortex_m3 = armv7m->arch_info; swjdp_common_t *swjdp = &cortex_m3->swjdp_info; +#ifdef ARMV7_GDB_HACKS + /* If the LR register is being modified, make sure it will put us + * in "thumb" mode, or an INVSTATE exception will occur. This is a + * hack to deal with the fact that gdb will sometimes "forge" + * return addresses, and doesn't set the LSB correctly (i.e., when + * printing expressions containing function calls, it sets LR=0.) */ + + if (num == 14) + value |= 0x01; +#endif + if ((type == ARMV7M_REGISTER_CORE_GP) && (num <= ARMV7M_PSP)) { retval = ahbap_write_coreregister_u32(swjdp, value, num); @@ -1185,23 +1249,31 @@ int cortex_m3_store_core_reg_u32(struct target_s *target, enum armv7m_regtype ty else if (type == ARMV7M_REGISTER_CORE_SP) /* Special purpose core register */ { /* write other registers */ - u32 savedram , tempr0; - u32 SYSm; - u32 instr; - SYSm = num & 0x1F; - ahbap_read_system_u32(swjdp, 0x20000000, &savedram); - instr = ARMV7M_T_MSR(SYSm, 0); - ahbap_write_system_u32(swjdp, 0x20000000, ARMV7M_T_MSR(SYSm, 0)); - ahbap_read_coreregister_u32(swjdp, &tempr0, 0); - ahbap_write_coreregister_u32(swjdp, value, 0); - ahbap_write_coreregister_u32(swjdp, 0x20000000, 15); - cortex_m3_single_step_core(target); - ahbap_write_coreregister_u32(swjdp, tempr0, 0); - armv7m->core_cache->reg_list[15].dirty = armv7m->core_cache->reg_list[15].valid; - ahbap_write_system_u32(swjdp, 0x20000000, savedram); - swjdp_transaction_endcheck(swjdp); - LOG_DEBUG("write special reg %i value 0x%x ", SYSm, value); + ahbap_read_coreregister_u32(swjdp, ®, 20); + + switch (num) + { + case 19: + buf_set_u32((u8*)®, 0, 8, value); + break; + + case 20: + buf_set_u32((u8*)®, 8, 8, value); + break; + + case 21: + buf_set_u32((u8*)®, 16, 8, value); + break; + + case 22: + buf_set_u32((u8*)®, 24, 8, value); + break; + } + + ahbap_write_coreregister_u32(swjdp, reg, 20); + + LOG_DEBUG("write special reg %i value 0x%x ", num, value); } else { @@ -1287,6 +1359,13 @@ void cortex_m3_build_reg_cache(target_t *target) int cortex_m3_init_target(struct command_context_s *cmd_ctx, struct target_s *target) { + cortex_m3_build_reg_cache(target); + return ERROR_OK; +} + +int cortex_m3_examine(struct target_s *target) +{ + int retval; u32 cpuid, fpcr, dwtcr, ictr; int i; @@ -1294,53 +1373,60 @@ int cortex_m3_init_target(struct command_context_s *cmd_ctx, struct target_s *ta armv7m_common_t *armv7m = target->arch_info; cortex_m3_common_t *cortex_m3 = armv7m->arch_info; swjdp_common_t *swjdp = &cortex_m3->swjdp_info; - - cortex_m3_build_reg_cache(target); - ahbap_debugport_init(swjdp); - - /* Read from Device Identification Registers */ - target_read_u32(target, CPUID, &cpuid); - if (((cpuid >> 4) & 0xc3f) == 0xc23) - LOG_DEBUG("CORTEX-M3 processor detected"); - LOG_DEBUG("cpuid: 0x%8.8x", cpuid); - - target_read_u32(target, NVIC_ICTR, &ictr); - cortex_m3->intlinesnum = (ictr & 0x1F) + 1; - cortex_m3->intsetenable = calloc(cortex_m3->intlinesnum, 4); - for (i = 0; i < cortex_m3->intlinesnum; i++) - { - target_read_u32(target, NVIC_ISE0 + 4 * i, cortex_m3->intsetenable + i); - LOG_DEBUG("interrupt enable[%i] = 0x%8.8x", i, cortex_m3->intsetenable[i]); - } - - /* Setup FPB */ - target_read_u32(target, FP_CTRL, &fpcr); - cortex_m3->auto_bp_type = 1; - cortex_m3->fp_num_code = (fpcr >> 4) & 0xF; - cortex_m3->fp_num_lit = (fpcr >> 8) & 0xF; - cortex_m3->fp_code_available = cortex_m3->fp_num_code; - cortex_m3->fp_comparator_list = calloc(cortex_m3->fp_num_code + cortex_m3->fp_num_lit, sizeof(cortex_m3_fp_comparator_t)); - for (i = 0; i < cortex_m3->fp_num_code + cortex_m3->fp_num_lit; i++) + + if ((retval = ahbap_debugport_init(swjdp)) != ERROR_OK) + return retval; + + if (!target->type->examined) { - cortex_m3->fp_comparator_list[i].type = (i < cortex_m3->fp_num_code) ? FPCR_CODE : FPCR_LITERAL; - cortex_m3->fp_comparator_list[i].fpcr_address = FP_COMP0 + 4 * i; - } - LOG_DEBUG("FPB fpcr 0x%x, numcode %i, numlit %i", fpcr, cortex_m3->fp_num_code, cortex_m3->fp_num_lit); + target->type->examined = 1; - /* Setup DWT */ - target_read_u32(target, DWT_CTRL, &dwtcr); - cortex_m3->dwt_num_comp = (dwtcr >> 28) & 0xF; - cortex_m3->dwt_comp_available = cortex_m3->dwt_num_comp; - cortex_m3->dwt_comparator_list=calloc(cortex_m3->dwt_num_comp, sizeof(cortex_m3_dwt_comparator_t)); - for (i = 0; i < cortex_m3->dwt_num_comp; i++) - { - cortex_m3->dwt_comparator_list[i].dwt_comparator_address = DWT_COMP0 + 0x10 * i; + /* Read from Device Identification Registers */ + if ((retval = target_read_u32(target, CPUID, &cpuid)) != ERROR_OK) + return retval; + + if (((cpuid >> 4) & 0xc3f) == 0xc23) + LOG_DEBUG("CORTEX-M3 processor detected"); + LOG_DEBUG("cpuid: 0x%8.8x", cpuid); + + target_read_u32(target, NVIC_ICTR, &ictr); + cortex_m3->intlinesnum = (ictr & 0x1F) + 1; + cortex_m3->intsetenable = calloc(cortex_m3->intlinesnum, 4); + for (i = 0; i < cortex_m3->intlinesnum; i++) + { + target_read_u32(target, NVIC_ISE0 + 4 * i, cortex_m3->intsetenable + i); + LOG_DEBUG("interrupt enable[%i] = 0x%8.8x", i, cortex_m3->intsetenable[i]); + } + + /* Setup FPB */ + target_read_u32(target, FP_CTRL, &fpcr); + cortex_m3->auto_bp_type = 1; + cortex_m3->fp_num_code = (fpcr >> 4) & 0xF; + cortex_m3->fp_num_lit = (fpcr >> 8) & 0xF; + cortex_m3->fp_code_available = cortex_m3->fp_num_code; + cortex_m3->fp_comparator_list = calloc(cortex_m3->fp_num_code + cortex_m3->fp_num_lit, sizeof(cortex_m3_fp_comparator_t)); + for (i = 0; i < cortex_m3->fp_num_code + cortex_m3->fp_num_lit; i++) + { + cortex_m3->fp_comparator_list[i].type = (i < cortex_m3->fp_num_code) ? FPCR_CODE : FPCR_LITERAL; + cortex_m3->fp_comparator_list[i].fpcr_address = FP_COMP0 + 4 * i; + } + LOG_DEBUG("FPB fpcr 0x%x, numcode %i, numlit %i", fpcr, cortex_m3->fp_num_code, cortex_m3->fp_num_lit); + + /* Setup DWT */ + target_read_u32(target, DWT_CTRL, &dwtcr); + cortex_m3->dwt_num_comp = (dwtcr >> 28) & 0xF; + cortex_m3->dwt_comp_available = cortex_m3->dwt_num_comp; + cortex_m3->dwt_comparator_list = calloc(cortex_m3->dwt_num_comp, sizeof(cortex_m3_dwt_comparator_t)); + for (i = 0; i < cortex_m3->dwt_num_comp; i++) + { + cortex_m3->dwt_comparator_list[i].dwt_comparator_address = DWT_COMP0 + 0x10 * i; + } } return ERROR_OK; } -int cortex_m3_quit() +int cortex_m3_quit(void) { return ERROR_OK; @@ -1388,6 +1474,8 @@ int cortex_m3_target_request_data(target_t *target, u32 size, u8 *buffer) int cortex_m3_handle_target_request(void *priv) { target_t *target = priv; + if (!target->type->examined) + return ERROR_OK; armv7m_common_t *armv7m = target->arch_info; cortex_m3_common_t *cortex_m3 = armv7m->arch_info; swjdp_common_t *swjdp = &cortex_m3->swjdp_info; @@ -1422,7 +1510,7 @@ int cortex_m3_handle_target_request(void *priv) return ERROR_OK; } -int cortex_m3_init_arch_info(target_t *target, cortex_m3_common_t *cortex_m3, int chain_pos, char *variant) +int cortex_m3_init_arch_info(target_t *target, cortex_m3_common_t *cortex_m3, int chain_pos, const char *variant) { armv7m_common_t *armv7m; armv7m = &cortex_m3->armv7m; @@ -1450,6 +1538,15 @@ int cortex_m3_init_arch_info(target_t *target, cortex_m3_common_t *cortex_m3, in armv7m->pre_restore_context = NULL; armv7m->post_restore_context = NULL; + if (variant) + { + cortex_m3->variant = strdup(variant); + } + else + { + cortex_m3->variant = strdup(""); + } + armv7m_init_arch_info(target, armv7m); armv7m->arch_info = cortex_m3; armv7m->load_core_reg_u32 = cortex_m3_load_core_reg_u32; @@ -1460,27 +1557,11 @@ int cortex_m3_init_arch_info(target_t *target, cortex_m3_common_t *cortex_m3, in return ERROR_OK; } -/* target cortex_m3 */ -int cortex_m3_target_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, struct target_s *target) +int cortex_m3_target_create(struct target_s *target, Jim_Interp *interp) { - int chain_pos; - char *variant = NULL; - cortex_m3_common_t *cortex_m3 = malloc(sizeof(cortex_m3_common_t)); - memset(cortex_m3, 0, sizeof(*cortex_m3)); - - if (argc < 4) - { - LOG_ERROR("'target cortex_m3' requires at least one additional argument"); - exit(-1); - } - - chain_pos = strtoul(args[3], NULL, 0); + cortex_m3_common_t *cortex_m3 = calloc(1,sizeof(cortex_m3_common_t)); - if (argc >= 5) - variant = args[4]; - - cortex_m3_init_arch_info(target, cortex_m3, chain_pos, variant); - cortex_m3_register_commands(cmd_ctx); + cortex_m3_init_arch_info(target, cortex_m3, target->chain_position, target->variant); return ERROR_OK; } @@ -1488,8 +1569,46 @@ int cortex_m3_target_command(struct command_context_s *cmd_ctx, char *cmd, char int cortex_m3_register_commands(struct command_context_s *cmd_ctx) { int retval; + command_t *cortex_m3_cmd; retval = armv7m_register_commands(cmd_ctx); + cortex_m3_cmd = register_command(cmd_ctx, NULL, "cortex_m3", NULL, COMMAND_ANY, "cortex_m3 specific commands"); + register_command(cmd_ctx, cortex_m3_cmd, "maskisr", handle_cortex_m3_mask_interrupts_command, COMMAND_EXEC, "mask cortex_m3 interrupts ['on'|'off']"); + return retval; } + +int handle_cortex_m3_mask_interrupts_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc) +{ + target_t *target = get_current_target(cmd_ctx); + armv7m_common_t *armv7m = target->arch_info; + cortex_m3_common_t *cortex_m3 = armv7m->arch_info; + + if (target->state != TARGET_HALTED) + { + command_print(cmd_ctx, "target must be stopped for \"%s\" command", cmd); + return ERROR_OK; + } + + if (argc > 0) + { + if (!strcmp(args[0], "on")) + { + cortex_m3_write_debug_halt_mask(target, C_HALT|C_MASKINTS, 0); + } + else if (!strcmp(args[0], "off")) + { + cortex_m3_write_debug_halt_mask(target, C_HALT, C_MASKINTS); + } + else + { + command_print(cmd_ctx, "usage: cortex_m3 maskisr ['on'|'off']"); + } + } + + command_print(cmd_ctx, "cortex_m3 interrupt mask %s", + (cortex_m3->dcb_dhcsr & C_MASKINTS) ? "on" : "off"); + + return ERROR_OK; +}