X-Git-Url: https://review.openocd.org/gitweb?a=blobdiff_plain;f=src%2Ftarget%2Fcortex_m3.c;h=3f347697bd41a8ca76836f3e446225f5daa11fbd;hb=3d3128a8f5bb15f1d05ac5eb7ecc5e692ae290ce;hp=762e3184c901151aedc230f8011919c3f07def2e;hpb=0c3a4b4d818554ea00dc993d31cea9f3e0d1a87d;p=openocd.git

diff --git a/src/target/cortex_m3.c b/src/target/cortex_m3.c
index 762e3184c9..3f347697bd 100644
--- a/src/target/cortex_m3.c
+++ b/src/target/cortex_m3.c
@@ -80,7 +80,7 @@ static int cortexm3_dap_read_coreregister_u32(struct swjdp_common *swjdp,
 	dap_setup_accessport(swjdp, CSW_32BIT | CSW_ADDRINC_OFF, DCB_DCRDR & 0xFFFFFFF0);
 	dap_ap_read_reg_u32(swjdp, AP_REG_BD0 | (DCB_DCRDR & 0xC), value);
 
-	retval = swjdp_transaction_endcheck(swjdp);
+	retval = jtagdp_transaction_endcheck(swjdp);
 
 	/* restore DCB_DCRDR - this needs to be in a seperate
 	 * transaction otherwise the emulated DCC channel breaks */
@@ -111,7 +111,7 @@ static int cortexm3_dap_write_coreregister_u32(struct swjdp_common *swjdp,
 	dap_setup_accessport(swjdp, CSW_32BIT | CSW_ADDRINC_OFF, DCB_DCRSR & 0xFFFFFFF0);
 	dap_ap_write_reg_u32(swjdp, AP_REG_BD0 | (DCB_DCRSR & 0xC), regnum | DCRSR_WnR);
 
-	retval = swjdp_transaction_endcheck(swjdp);
+	retval = jtagdp_transaction_endcheck(swjdp);
 
 	/* restore DCB_DCRDR - this needs to be in a seperate
 	 * transaction otherwise the emulated DCC channel breaks */
@@ -238,7 +238,7 @@ static int cortex_m3_endreset_event(struct target *target)
 		target_write_u32(target, dwt_list[i].dwt_comparator_address + 8,
 				dwt_list[i].function);
 	}
-	swjdp_transaction_endcheck(swjdp);
+	jtagdp_transaction_endcheck(swjdp);
 
 	register_cache_invalidate(cortex_m3->armv7m.core_cache);
 
@@ -317,7 +317,7 @@ static int cortex_m3_examine_exception_reason(struct target *target)
 			except_sr = 0;
 			break;
 	}
-	swjdp_transaction_endcheck(swjdp);
+	jtagdp_transaction_endcheck(swjdp);
 	LOG_DEBUG("%s SHCSR 0x%" PRIx32 ", SR 0x%" PRIx32 ", CFSR 0x%" PRIx32 ", AR 0x%" PRIx32 "", armv7m_exception_string(armv7m->exception_number), \
 		shcsr, except_sr, cfsr, except_ar);
 	return ERROR_OK;
@@ -416,6 +416,21 @@ static int cortex_m3_poll(struct target *target)
 		return retval;
 	}
 
+	/* Recover from lockup.  See ARMv7-M architecture spec,
+	 * section B1.5.15 "Unrecoverable exception cases".
+	 *
+	 * REVISIT Is there a better way to report and handle this?
+	 */
+	if (cortex_m3->dcb_dhcsr & S_LOCKUP) {
+		LOG_WARNING("%s -- clearing lockup after double fault",
+				target_name(target));
+		cortex_m3_write_debug_halt_mask(target, C_HALT, 0);
+		target->debug_reason = DBG_REASON_DBGRQ;
+
+		/* refresh status bits */
+		mem_ap_read_atomic_u32(swjdp, DCB_DHCSR, &cortex_m3->dcb_dhcsr);
+	}
+
 	if (cortex_m3->dcb_dhcsr & S_RESET_ST)
 	{
 		/* check if still in reset */
@@ -1675,8 +1690,8 @@ static int cortex_m3_examine(struct target *target)
 			return retval;
 
 		if (((cpuid >> 4) & 0xc3f) == 0xc23)
-			LOG_DEBUG("Cortex-M3 r%dp%d processor detected",
-				(cpuid >> 20) & 0xf, (cpuid >> 0) & 0xf);
+			LOG_DEBUG("Cortex-M3 r%" PRId8 "p%" PRId8 " processor detected",
+				(uint8_t)((cpuid >> 20) & 0xf), (uint8_t)((cpuid >> 0) & 0xf));
 		LOG_DEBUG("cpuid: 0x%8.8" PRIx32 "", cpuid);
 
 		/* NOTE: FPB and DWT are both optional. */