X-Git-Url: https://review.openocd.org/gitweb?a=blobdiff_plain;f=src%2Ftarget%2Fcortex_m3.c;h=3a567abae43d699cb3e6d62927a65405524607f0;hb=007e9e2d60ac6e23e7e74bfc6bcf009d7e029fb6;hp=db9dd0547fa7e24214cc1b02cb006f62803a5edc;hpb=a34e4b39c47cd9f67f3f70be36c1b2f25ab23f5f;p=openocd.git

diff --git a/src/target/cortex_m3.c b/src/target/cortex_m3.c
index db9dd0547f..3a567abae4 100644
--- a/src/target/cortex_m3.c
+++ b/src/target/cortex_m3.c
@@ -1,6 +1,7 @@
 /***************************************************************************
  *   Copyright (C) 2005 by Dominic Rath                                    *
  *   Dominic.Rath@gmx.de                                                   *
+ *                                                                         *
  *   Copyright (C) 2006 by Magnus Lundin                                   *
  *   lundin@mlu.mine.nu                                                    *
  *                                                                         *
@@ -348,7 +349,7 @@ int cortex_m3_debug_entry(target_t *target)
 	return ERROR_OK;
 }
 
-enum target_state cortex_m3_poll(target_t *target)
+int cortex_m3_poll(target_t *target)
 {
 	int retval;
 	u32 prev_target_state = target->state;
@@ -363,7 +364,7 @@ enum target_state cortex_m3_poll(target_t *target)
 	if (retval != ERROR_OK)
 	{
 		target->state = TARGET_UNKNOWN;
-		return TARGET_UNKNOWN;
+		return retval;
 	}
 	
 	if (cortex_m3->dcb_dhcsr & S_RESET_ST)
@@ -374,7 +375,7 @@ enum target_state cortex_m3_poll(target_t *target)
 		if (cortex_m3->dcb_dhcsr & S_RESET_ST)
 		{
 			target->state = TARGET_RESET;
-			return target->state;
+			return ERROR_OK;
 		}
 	}
 	
@@ -394,7 +395,7 @@ enum target_state cortex_m3_poll(target_t *target)
 		if ((prev_target_state == TARGET_RUNNING) || (prev_target_state == TARGET_RESET))
 		{
 			if ((retval = cortex_m3_debug_entry(target)) != ERROR_OK)
-				return TARGET_UNKNOWN;
+				return retval;
 			
 			target_call_event_callbacks(target, TARGET_EVENT_HALTED);
 		}
@@ -402,7 +403,7 @@ enum target_state cortex_m3_poll(target_t *target)
 		{
 			DEBUG(" ");
 			if ((retval = cortex_m3_debug_entry(target)) != ERROR_OK)
-				return TARGET_UNKNOWN;
+				return retval;
 
 			target_call_event_callbacks(target, TARGET_EVENT_DEBUG_HALTED);
 		}
@@ -416,7 +417,7 @@ enum target_state cortex_m3_poll(target_t *target)
     /* Read Debug Fault Status Register, added to figure out the lockup when running flashtest.script  */
     ahbap_read_system_atomic_u32(swjdp, NVIC_DFSR, &cortex_m3->nvic_dfsr);
 	DEBUG("dcb_dhcsr 0x%x, nvic_dfsr 0x%x, target->state: %s", cortex_m3->dcb_dhcsr, cortex_m3->nvic_dfsr, target_state_strings[target->state]);	
-	return target->state;
+	return ERROR_OK;
 }
 
 int cortex_m3_halt(target_t *target)
@@ -1371,8 +1372,12 @@ int cortex_m3_dcc_read(swjdp_common_t *swjdp, u8 *value, u8 *ctrl)
 	
 	/* write ack back to software dcc register
 	 * signify we have read data */
-	dcrdr = 0;
-	ahbap_write_buf_u16( swjdp, (u8*)&dcrdr, 1, DCB_DCRDR);
+	if (dcrdr & (1 << 0))
+	{
+		dcrdr = 0;
+		ahbap_write_buf_u16( swjdp, (u8*)&dcrdr, 1, DCB_DCRDR);
+	}
+	
 	return ERROR_OK;
 }
 
@@ -1412,10 +1417,11 @@ int cortex_m3_handle_target_request(void *priv)
 		cortex_m3_dcc_read(swjdp, &data, &ctrl);
 		
 		/* check if we have data */
-		if (ctrl & (1<<0))
+		if (ctrl & (1 << 0))
 		{
 			u32 request;
 			
+			/* we assume target is quick enough */
 			request = data;
 			cortex_m3_dcc_read(swjdp, &data, &ctrl);
 			request |= (data << 8);