X-Git-Url: https://review.openocd.org/gitweb?a=blobdiff_plain;f=src%2Ftarget%2Fcortex_m3.c;h=255fcd03453c4cf770cf1831b515621062c04ac2;hb=18293612537125c8864d4627c7c4b2b4ba7cc882;hp=803f05ce89c5e7746881cb54e53ab035f266091e;hpb=cab29a63de935871135a6ee0ed9d29d5edea0f27;p=openocd.git

diff --git a/src/target/cortex_m3.c b/src/target/cortex_m3.c
index 803f05ce89..255fcd0345 100644
--- a/src/target/cortex_m3.c
+++ b/src/target/cortex_m3.c
@@ -51,7 +51,7 @@ int cortex_m3_quit();
 int cortex_m3_load_core_reg_u32(target_t *target, enum armv7m_regtype type, u32 num, u32 *value);
 int cortex_m3_store_core_reg_u32(target_t *target, enum armv7m_regtype type, u32 num, u32 value);
 int cortex_m3_target_request_data(target_t *target, u32 size, u8 *buffer);
-int cortex_m3_examine(struct command_context_s *cmd_ctx, struct target_s *target);
+int cortex_m3_examine(struct target_s *target);
 
 #ifdef ARMV7_GDB_HACKS
 extern u8 armv7m_gdb_dummy_cpsr_value[];
@@ -81,6 +81,7 @@ target_type_t cortexm3_target =
 	.write_memory = cortex_m3_write_memory,
 	.bulk_write_memory = cortex_m3_bulk_write_memory,
 	.checksum_memory = armv7m_checksum_memory,
+	.blank_check_memory = armv7m_blank_check_memory,
 	
 	.run_algorithm = armv7m_run_algorithm,
 	
@@ -673,6 +674,7 @@ int cortex_m3_assert_reset(target_t *target)
 	armv7m_common_t *armv7m = target->arch_info;
 	cortex_m3_common_t *cortex_m3 = armv7m->arch_info;
 	swjdp_common_t *swjdp = &cortex_m3->swjdp_info;
+	int assert_srst = 1;
 	
 	LOG_DEBUG("target->state: %s", target_state_strings[target->state]);
 	
@@ -689,7 +691,7 @@ int cortex_m3_assert_reset(target_t *target)
 		
 	ahbap_write_system_u32(swjdp, DCB_DCRDR, 0 );
 	
-	if (target->reset_mode == RESET_RUN)
+	if (!target->reset_halt)
 	{
 		/* Set/Clear C_MASKINTS in a separate operation */
 		if (cortex_m3->dcb_dhcsr & C_MASKINTS)
@@ -706,13 +708,53 @@ int cortex_m3_assert_reset(target_t *target)
 		ahbap_write_system_atomic_u32(swjdp, DCB_DEMCR, TRCENA | VC_HARDERR | VC_BUSERR | VC_CORERESET );
 	}
 	
-	if (jtag_reset_config & RESET_SRST_PULLS_TRST)
+	/* following hack is to handle luminary reset
+	 * when srst is asserted the luminary device seesm to also clear the debug registers
+	 * which does not match the armv7 debug TRM */
+		
+	if (strcmp(cortex_m3->variant, "lm3s") == 0)
 	{
-		jtag_add_reset(1, 1);
+		/* get revision of lm3s target, only early silicon has this issue
+		 * Fury Rev B, DustDevil Rev B, Tempest all ok */
+		
+		u32 did0;
+		
+		if (target_read_u32(target, 0x400fe000, &did0) == ERROR_OK)
+		{
+			switch ((did0 >> 16) & 0xff)
+			{
+				case 0:
+					/* all Sandstorm suffer issue */
+					assert_srst = 0;
+					break;
+				
+				case 1:
+				case 3:
+					/* only Fury/DustDevil rev A suffer reset problems */
+					if (((did0 >> 8) & 0xff) == 0)
+						assert_srst = 0;
+					break;
+			}
+		}
+	}
+	
+	if (assert_srst)
+	{
+		/* default to asserting srst */
+		if (jtag_reset_config & RESET_SRST_PULLS_TRST)
+		{
+			jtag_add_reset(1, 1);
+		}
+		else
+		{
+			jtag_add_reset(0, 1);
+		}
 	}
 	else
 	{
-		jtag_add_reset(0, 1);
+		/* this causes the luminary device to reset using the watchdog */
+		ahbap_write_system_atomic_u32(swjdp, NVIC_AIRCR, AIRCR_VECTKEY | AIRCR_SYSRESETREQ );
+		LOG_DEBUG("Using Luminary Reset: SYSRESETREQ");
 	}
 	
 	target->state = TARGET_RESET;
@@ -720,6 +762,13 @@ int cortex_m3_assert_reset(target_t *target)
 	
 	armv7m_invalidate_core_regs(target);
 
+    if (target->reset_halt)
+    {
+    	int retval;
+		if ((retval = target_halt(target))!=ERROR_OK)
+			return retval;
+    }
+	
 	return ERROR_OK;
 }
 
@@ -1265,7 +1314,7 @@ int cortex_m3_init_target(struct command_context_s *cmd_ctx, struct target_s *ta
 	return ERROR_OK;
 }
 
-int cortex_m3_examine(struct command_context_s *cmd_ctx, struct target_s *target)
+int cortex_m3_examine(struct target_s *target)
 {
 	int retval;
 	u32 cpuid, fpcr, dwtcr, ictr;
@@ -1325,7 +1374,6 @@ int cortex_m3_examine(struct command_context_s *cmd_ctx, struct target_s *target
 	return ERROR_OK;
 }
 
-
 int cortex_m3_quit()
 {
 	
@@ -1438,6 +1486,15 @@ int cortex_m3_init_arch_info(target_t *target, cortex_m3_common_t *cortex_m3, in
 	armv7m->pre_restore_context = NULL;
 	armv7m->post_restore_context = NULL;
 	
+	if (variant)
+	{
+		cortex_m3->variant = strdup(variant);
+	}
+	else
+	{
+		cortex_m3->variant = strdup("");
+	}
+	
 	armv7m_init_arch_info(target, armv7m);	
 	armv7m->arch_info = cortex_m3;
 	armv7m->load_core_reg_u32 = cortex_m3_load_core_reg_u32;
@@ -1468,7 +1525,6 @@ int cortex_m3_target_command(struct command_context_s *cmd_ctx, char *cmd, char
 		variant = args[4];
 	
 	cortex_m3_init_arch_info(target, cortex_m3, chain_pos, variant);
-	cortex_m3_register_commands(cmd_ctx);
 	
 	return ERROR_OK;
 }
@@ -1481,4 +1537,3 @@ int cortex_m3_register_commands(struct command_context_s *cmd_ctx)
 	
 	return retval;
 }
-