X-Git-Url: https://review.openocd.org/gitweb?a=blobdiff_plain;f=src%2Ftarget%2Fcortex_m.c;h=4cc61f64befc71a9d79fcd22da27edf52b46277c;hb=24c0f9470a77e3396102272b041810b45baba47b;hp=acf280505c4dccf9429c7d13ab18815eea875bf8;hpb=ec5e4bae251e01d2b7681e370a6c5e82a81e5962;p=openocd.git

diff --git a/src/target/cortex_m.c b/src/target/cortex_m.c
index acf280505c..4cc61f64be 100644
--- a/src/target/cortex_m.c
+++ b/src/target/cortex_m.c
@@ -1570,6 +1570,12 @@ static int cortex_m3_read_memory(struct target *target, uint32_t address,
 	struct adiv5_dap *swjdp = &armv7m->dap;
 	int retval = ERROR_COMMAND_SYNTAX_ERROR;
 
+	if (armv7m->arm.is_armv6m) {
+		/* armv6m does not handle unaligned memory access */
+		if (((size == 4) && (address & 0x3u)) || ((size == 2) && (address & 0x1u)))
+			return ERROR_TARGET_UNALIGNED_ACCESS;
+	}
+
 	/* cortex_m3 handles unaligned memory access */
 	if (count && buffer) {
 		switch (size) {
@@ -1595,6 +1601,12 @@ static int cortex_m3_write_memory(struct target *target, uint32_t address,
 	struct adiv5_dap *swjdp = &armv7m->dap;
 	int retval = ERROR_COMMAND_SYNTAX_ERROR;
 
+	if (armv7m->arm.is_armv6m) {
+		/* armv6m does not handle unaligned memory access */
+		if (((size == 4) && (address & 0x3u)) || ((size == 2) && (address & 0x1u)))
+			return ERROR_TARGET_UNALIGNED_ACCESS;
+	}
+
 	if (count && buffer) {
 		switch (size) {
 			case 4:
@@ -1812,6 +1824,14 @@ int cortex_m3_examine(struct target *target)
 				LOG_DEBUG("Cortex-M%d floating point feature FPv4_SP found", i);
 				armv7m->fp_feature = FPv4_SP;
 			}
+		} else if (i == 0) {
+			/* Cortex-M0 does not support unaligned memory access */
+			armv7m->arm.is_armv6m = true;
+		}
+
+		if (i == 4 || i == 3) {
+			/* Cortex-M3/M4 has 4096 bytes autoincrement range */
+			armv7m->dap.tar_autoincr_block = (1 << 12);
 		}
 
 		/* NOTE: FPB and DWT are both optional. */
@@ -1949,8 +1969,11 @@ static int cortex_m3_init_arch_info(struct target *target,
 	/* Leave (only) generic DAP stuff for debugport_init(); */
 	armv7m->dap.jtag_info = &cortex_m3->jtag_info;
 	armv7m->dap.memaccess_tck = 8;
-	/* Cortex-M3 has 4096 bytes autoincrement range */
-	armv7m->dap.tar_autoincr_block = (1 << 12);
+
+	/* Cortex-M3/M4 has 4096 bytes autoincrement range
+	 * but set a safe default to 1024 to support Cortex-M0
+	 * this will be changed in cortex_m3_examine if a M3/M4 is detected */
+	armv7m->dap.tar_autoincr_block = (1 << 10);
 
 	/* register arch-specific functions */
 	armv7m->examine_debug_reason = cortex_m3_examine_debug_reason;