X-Git-Url: https://review.openocd.org/gitweb?a=blobdiff_plain;f=src%2Ftarget%2Fcortex_a8.c;h=bcdb526017dc3063972d82c2b4747a7bc5b4de4f;hb=75cfda4cd1fe057f0557bd86963a71e530edd584;hp=e312e547615842bd45259705a7064f3320530de5;hpb=5949a3b3a55d987008b63b80af42c08601babb75;p=openocd.git diff --git a/src/target/cortex_a8.c b/src/target/cortex_a8.c index e312e54761..bcdb526017 100644 --- a/src/target/cortex_a8.c +++ b/src/target/cortex_a8.c @@ -38,10 +38,11 @@ #include "register.h" #include "target_request.h" #include "target_type.h" +#include "arm_opcodes.h" static int cortex_a8_poll(struct target *target); static int cortex_a8_debug_entry(struct target *target); -static int cortex_a8_restore_context(struct target *target); +static int cortex_a8_restore_context(struct target *target, bool bpwp); static int cortex_a8_set_breakpoint(struct target *target, struct breakpoint *breakpoint, uint8_t matchmode); static int cortex_a8_unset_breakpoint(struct target *target, @@ -91,8 +92,8 @@ static int cortex_a8_init_debug_access(struct target *target) /* To reduce needless round-trips, pass in a pointer to the current * DSCR value. Initialize it to zero if you just need to know the - * value on return from this function; or (1 << DSCR_INSTR_COMP) if - * you happen to know that no instruction is pending. + * value on return from this function; or DSCR_INSTR_COMP if you + * happen to know that no instruction is pending. */ static int cortex_a8_exec_opcode(struct target *target, uint32_t opcode, uint32_t *dscr_p) @@ -107,7 +108,7 @@ static int cortex_a8_exec_opcode(struct target *target, LOG_DEBUG("exec opcode 0x%08" PRIx32, opcode); /* Wait for InstrCompl bit to be set */ - while ((dscr & (1 << DSCR_INSTR_COMP)) == 0) + while ((dscr & DSCR_INSTR_COMP) == 0) { retval = mem_ap_read_atomic_u32(swjdp, armv7a->debug_base + CPUDBG_DSCR, &dscr); @@ -130,7 +131,7 @@ static int cortex_a8_exec_opcode(struct target *target, return retval; } } - while ((dscr & (1 << DSCR_INSTR_COMP)) == 0); /* Wait for InstrCompl bit to be set */ + while ((dscr & DSCR_INSTR_COMP) == 0); /* Wait for InstrCompl bit to be set */ if (dscr_p) *dscr_p = dscr; @@ -198,7 +199,7 @@ static int cortex_a8_dap_read_coreregister_u32(struct target *target, } /* Wait for DTRRXfull then read DTRRTX */ - while ((dscr & (1 << DSCR_DTR_TX_FULL)) == 0) + while ((dscr & DSCR_DTR_TX_FULL) == 0) { retval = mem_ap_read_atomic_u32(swjdp, armv7a->debug_base + CPUDBG_DSCR, &dscr); @@ -225,7 +226,7 @@ static int cortex_a8_dap_write_coreregister_u32(struct target *target, /* Check that DCCRX is not full */ retval = mem_ap_read_atomic_u32(swjdp, armv7a->debug_base + CPUDBG_DSCR, &dscr); - if (dscr & (1 << DSCR_DTR_RX_FULL)) + if (dscr & DSCR_DTR_RX_FULL) { LOG_ERROR("DSCR_DTR_RX_FULL, dscr 0x%08" PRIx32, dscr); /* Clear DCCRX with MCR(p14, 0, Rd, c0, c5, 0), opcode 0xEE000E15 */ @@ -315,14 +316,14 @@ static int cortex_a8_read_dcc(struct cortex_a8_common *a8, uint32_t *data, uint32_t *dscr_p) { struct swjdp_common *swjdp = &a8->armv7a_common.swjdp_info; - uint32_t dscr = 1 << DSCR_INSTR_COMP; + uint32_t dscr = DSCR_INSTR_COMP; int retval; if (dscr_p) dscr = *dscr_p; /* Wait for DTRRXfull */ - while ((dscr & (1 << DSCR_DTR_TX_FULL)) == 0) { + while ((dscr & DSCR_DTR_TX_FULL) == 0) { retval = mem_ap_read_atomic_u32(swjdp, a8->armv7a_common.debug_base + CPUDBG_DSCR, &dscr); @@ -350,10 +351,10 @@ static int cortex_a8_dpm_prepare(struct arm_dpm *dpm) retval = mem_ap_read_atomic_u32(swjdp, a8->armv7a_common.debug_base + CPUDBG_DSCR, &dscr); - } while ((dscr & (1 << DSCR_INSTR_COMP)) == 0); + } while ((dscr & DSCR_INSTR_COMP) == 0); /* this "should never happen" ... */ - if (dscr & (1 << DSCR_DTR_RX_FULL)) { + if (dscr & DSCR_DTR_RX_FULL) { LOG_ERROR("DSCR_DTR_RX_FULL, dscr 0x%08" PRIx32, dscr); /* Clear DCCRX */ retval = cortex_a8_exec_opcode( @@ -376,7 +377,7 @@ static int cortex_a8_instr_write_data_dcc(struct arm_dpm *dpm, { struct cortex_a8_common *a8 = dpm_to_a8(dpm); int retval; - uint32_t dscr = 1 << DSCR_INSTR_COMP; + uint32_t dscr = DSCR_INSTR_COMP; retval = cortex_a8_write_dcc(a8, data); @@ -390,7 +391,7 @@ static int cortex_a8_instr_write_data_r0(struct arm_dpm *dpm, uint32_t opcode, uint32_t data) { struct cortex_a8_common *a8 = dpm_to_a8(dpm); - uint32_t dscr = 1 << DSCR_INSTR_COMP; + uint32_t dscr = DSCR_INSTR_COMP; int retval; retval = cortex_a8_write_dcc(a8, data); @@ -413,7 +414,7 @@ static int cortex_a8_instr_write_data_r0(struct arm_dpm *dpm, static int cortex_a8_instr_cpsr_sync(struct arm_dpm *dpm) { struct target *target = dpm->arm->target; - uint32_t dscr = 1 << DSCR_INSTR_COMP; + uint32_t dscr = DSCR_INSTR_COMP; /* "Prefetch flush" after modifying execution status in CPSR */ return cortex_a8_exec_opcode(target, @@ -426,7 +427,7 @@ static int cortex_a8_instr_read_data_dcc(struct arm_dpm *dpm, { struct cortex_a8_common *a8 = dpm_to_a8(dpm); int retval; - uint32_t dscr = 1 << DSCR_INSTR_COMP; + uint32_t dscr = DSCR_INSTR_COMP; /* the opcode, writing data to DCC */ retval = cortex_a8_exec_opcode( @@ -442,7 +443,7 @@ static int cortex_a8_instr_read_data_r0(struct arm_dpm *dpm, uint32_t opcode, uint32_t *data) { struct cortex_a8_common *a8 = dpm_to_a8(dpm); - uint32_t dscr = 1 << DSCR_INSTR_COMP; + uint32_t dscr = DSCR_INSTR_COMP; int retval; /* the opcode, writing data to R0 */ @@ -460,9 +461,70 @@ static int cortex_a8_instr_read_data_r0(struct arm_dpm *dpm, return cortex_a8_read_dcc(a8, data, &dscr); } +static int cortex_a8_bpwp_enable(struct arm_dpm *dpm, unsigned index, + uint32_t addr, uint32_t control) +{ + struct cortex_a8_common *a8 = dpm_to_a8(dpm); + uint32_t vr = a8->armv7a_common.debug_base; + uint32_t cr = a8->armv7a_common.debug_base; + int retval; + + switch (index) { + case 0 ... 15: /* breakpoints */ + vr += CPUDBG_BVR_BASE; + cr += CPUDBG_BCR_BASE; + break; + case 16 ... 31: /* watchpoints */ + vr += CPUDBG_WVR_BASE; + cr += CPUDBG_WCR_BASE; + index -= 16; + break; + default: + return ERROR_FAIL; + } + vr += 4 * index; + cr += 4 * index; + + LOG_DEBUG("A8: bpwp enable, vr %08x cr %08x", + (unsigned) vr, (unsigned) cr); + + retval = cortex_a8_dap_write_memap_register_u32(dpm->arm->target, + vr, addr); + if (retval != ERROR_OK) + return retval; + retval = cortex_a8_dap_write_memap_register_u32(dpm->arm->target, + cr, control); + return retval; +} + +static int cortex_a8_bpwp_disable(struct arm_dpm *dpm, unsigned index) +{ + struct cortex_a8_common *a8 = dpm_to_a8(dpm); + uint32_t cr; + + switch (index) { + case 0 ... 15: + cr = a8->armv7a_common.debug_base + CPUDBG_BCR_BASE; + break; + case 16 ... 31: + cr = a8->armv7a_common.debug_base + CPUDBG_WCR_BASE; + index -= 16; + break; + default: + return ERROR_FAIL; + } + cr += 4 * index; + + LOG_DEBUG("A8: bpwp disable, cr %08x", (unsigned) cr); + + /* clear control register */ + return cortex_a8_dap_write_memap_register_u32(dpm->arm->target, cr, 0); +} + static int cortex_a8_dpm_setup(struct cortex_a8_common *a8, uint32_t didr) { struct arm_dpm *dpm = &a8->armv7a_common.dpm; + int retval; dpm->arm = &a8->armv7a_common.armv4_5_common; dpm->didr = didr; @@ -477,7 +539,14 @@ static int cortex_a8_dpm_setup(struct cortex_a8_common *a8, uint32_t didr) dpm->instr_read_data_dcc = cortex_a8_instr_read_data_dcc; dpm->instr_read_data_r0 = cortex_a8_instr_read_data_r0; - return arm_dpm_setup(dpm); + dpm->bpwp_enable = cortex_a8_bpwp_enable; + dpm->bpwp_disable = cortex_a8_bpwp_disable; + + retval = arm_dpm_setup(dpm); + if (retval == ERROR_OK) + retval = arm_dpm_initialize(dpm); + + return retval; } @@ -571,7 +640,7 @@ static int cortex_a8_halt(struct target *target) */ mem_ap_read_atomic_u32(swjdp, armv7a->debug_base + CPUDBG_DSCR, &dscr); retval = mem_ap_write_atomic_u32(swjdp, - armv7a->debug_base + CPUDBG_DSCR, dscr | (1 << DSCR_HALT_DBG_MODE)); + armv7a->debug_base + CPUDBG_DSCR, dscr | DSCR_HALT_DBG_MODE); if (retval != ERROR_OK) goto out; @@ -579,7 +648,7 @@ static int cortex_a8_halt(struct target *target) do { mem_ap_read_atomic_u32(swjdp, armv7a->debug_base + CPUDBG_DSCR, &dscr); - } while ((dscr & (1 << DSCR_CORE_HALTED)) == 0); + } while ((dscr & DSCR_CORE_HALTED) == 0); target->debug_reason = DBG_REASON_DBGRQ; @@ -602,11 +671,7 @@ static int cortex_a8_resume(struct target *target, int current, dap_ap_select(swjdp, swjdp_debugap); if (!debug_execution) - { target_free_all_working_areas(target); -// cortex_m3_enable_breakpoints(target); -// cortex_m3_enable_watchpoints(target); - } #if 0 if (debug_execution) @@ -641,17 +706,17 @@ static int cortex_a8_resume(struct target *target, int current, */ switch (armv4_5->core_state) { - case ARMV4_5_STATE_ARM: + case ARM_STATE_ARM: resume_pc &= 0xFFFFFFFC; break; - case ARMV4_5_STATE_THUMB: + case ARM_STATE_THUMB: case ARM_STATE_THUMB_EE: /* When the return address is loaded into PC * bit 0 must be 1 to stay in Thumb state */ resume_pc |= 0x1; break; - case ARMV4_5_STATE_JAZELLE: + case ARM_STATE_JAZELLE: LOG_ERROR("How do I resume into Jazelle state??"); return ERROR_FAIL; } @@ -661,7 +726,7 @@ static int cortex_a8_resume(struct target *target, int current, armv4_5->core_cache->reg_list[15].dirty = 1; armv4_5->core_cache->reg_list[15].valid = 1; - cortex_a8_restore_context(target); + cortex_a8_restore_context(target, handle_breakpoints); #if 0 /* the front-end may request us not to handle breakpoints */ @@ -678,13 +743,18 @@ static int cortex_a8_resume(struct target *target, int current, } #endif - /* Restart core and wait for it to be started */ + /* Restart core and wait for it to be started + * NOTE: this clears DSCR_ITR_EN and other bits. + * + * REVISIT: for single stepping, we probably want to + * disable IRQs by default, with optional override... + */ mem_ap_write_atomic_u32(swjdp, armv7a->debug_base + CPUDBG_DRCR, 0x2); do { mem_ap_read_atomic_u32(swjdp, armv7a->debug_base + CPUDBG_DSCR, &dscr); - } while ((dscr & (1 << DSCR_CORE_RESTARTED)) == 0); + } while ((dscr & DSCR_CORE_RESTARTED) == 0); target->debug_reason = DBG_REASON_NOTHALTED; target->state = TARGET_RUNNING; @@ -713,7 +783,7 @@ static int cortex_a8_resume(struct target *target, int current, static int cortex_a8_debug_entry(struct target *target) { int i; - uint32_t regfile[16], pc, cpsr, dscr; + uint32_t regfile[16], cpsr, dscr; int retval = ERROR_OK; struct working_area *regfile_working_area = NULL; struct cortex_a8_common *cortex_a8 = target_to_cortex_a8(target); @@ -724,7 +794,7 @@ static int cortex_a8_debug_entry(struct target *target) LOG_DEBUG("dscr = 0x%08" PRIx32, cortex_a8->cpudbg_dscr); - /* Enable the ITR execution once we are in debug mode */ + /* REVISIT surely we should not re-read DSCR !! */ mem_ap_read_atomic_u32(swjdp, armv7a->debug_base + CPUDBG_DSCR, &dscr); @@ -733,31 +803,22 @@ static int cortex_a8_debug_entry(struct target *target) * Synchronization Barrier: ARMV4_5_MCR(15, 0, 0, 7, 10, 4). */ - dscr |= (1 << DSCR_EXT_INT_EN); + /* Enable the ITR execution once we are in debug mode */ + dscr |= DSCR_ITR_EN; retval = mem_ap_write_atomic_u32(swjdp, armv7a->debug_base + CPUDBG_DSCR, dscr); /* Examine debug reason */ - switch ((cortex_a8->cpudbg_dscr >> 2)&0xF) - { - case 0: /* DRCR[0] write */ - case 4: /* EDBGRQ */ - target->debug_reason = DBG_REASON_DBGRQ; - break; - case 1: /* HW breakpoint */ - case 3: /* SW BKPT */ - case 5: /* vector catch */ - target->debug_reason = DBG_REASON_BREAKPOINT; - break; - case 10: /* precise watchpoint */ - target->debug_reason = DBG_REASON_WATCHPOINT; - /* REVISIT could collect WFAR later, to see just - * which instruction triggered the watchpoint. - */ - break; - default: - target->debug_reason = DBG_REASON_UNDEFINED; - break; + arm_dpm_report_dscr(&armv7a->dpm, cortex_a8->cpudbg_dscr); + + /* save address of instruction that triggered the watchpoint? */ + if (target->debug_reason == DBG_REASON_WATCHPOINT) { + uint32_t wfar; + + retval = mem_ap_read_atomic_u32(swjdp, + armv7a->debug_base + CPUDBG_WFAR, + &wfar); + arm_dpm_report_wfar(&armv7a->dpm, wfar); } /* REVISIT fast_reg_read is never set ... */ @@ -781,7 +842,6 @@ static int cortex_a8_debug_entry(struct target *target) /* read Current PSR */ cortex_a8_dap_read_coreregister_u32(target, &cpsr, 16); - pc = regfile[15]; dap_ap_select(swjdp, swjdp_debugap); LOG_DEBUG("cpsr: %8.8" PRIx32, cpsr); @@ -832,10 +892,7 @@ static int cortex_a8_debug_entry(struct target *target) if (armv7a->post_debug_entry) armv7a->post_debug_entry(target); - - return retval; - } static void cortex_a8_post_debug_entry(struct target *target) @@ -918,7 +975,7 @@ static int cortex_a8_step(struct target *target, int current, uint32_t address, /* Setup single step breakpoint */ stepbreakpoint.address = address; - stepbreakpoint.length = (armv4_5->core_state == ARMV4_5_STATE_THUMB) + stepbreakpoint.length = (armv4_5->core_state == ARM_STATE_THUMB) ? 2 : 4; stepbreakpoint.type = BKPT_HARD; stepbreakpoint.set = 0; @@ -941,7 +998,8 @@ static int cortex_a8_step(struct target *target, int current, uint32_t address, } cortex_a8_unset_breakpoint(target, &stepbreakpoint); - if (timeout > 0) target->debug_reason = DBG_REASON_BREAKPOINT; + if (timeout > 0) + target->debug_reason = DBG_REASON_BREAKPOINT; if (breakpoint) cortex_a8_set_breakpoint(target, breakpoint, 0); @@ -952,7 +1010,7 @@ static int cortex_a8_step(struct target *target, int current, uint32_t address, return ERROR_OK; } -static int cortex_a8_restore_context(struct target *target) +static int cortex_a8_restore_context(struct target *target, bool bpwp) { struct armv7a_common *armv7a = target_to_armv7a(target); @@ -961,7 +1019,7 @@ static int cortex_a8_restore_context(struct target *target) if (armv7a->pre_restore_context) armv7a->pre_restore_context(target); - arm_dpm_write_dirty_registers(&armv7a->dpm); + arm_dpm_write_dirty_registers(&armv7a->dpm, bpwp); if (armv7a->post_restore_context) armv7a->post_restore_context(target); @@ -1280,6 +1338,8 @@ static int cortex_a8_write_memory(struct target *target, uint32_t address, * * For both ICache and DCache, walk all cache lines in the * address range. Cortex-A8 has fixed 64 byte line length. + * + * REVISIT per ARMv7, these may trigger watchpoints ... */ /* invalidate I-Cache */ @@ -1401,7 +1461,8 @@ static int cortex_a8_examine_first(struct target *target) int retval = ERROR_OK; uint32_t didr, ctypr, ttypr, cpuid; - LOG_DEBUG("TODO"); + /* stop assuming this is an OMAP! */ + LOG_DEBUG("TODO - autoconfigure"); /* Here we shall insert a proper ROM Table scan */ armv7a->debug_base = OMAP3530_DEBUG_BASE; @@ -1414,28 +1475,28 @@ static int cortex_a8_examine_first(struct target *target) if ((retval = mem_ap_read_atomic_u32(swjdp, armv7a->debug_base + CPUDBG_CPUID, &cpuid)) != ERROR_OK) { - LOG_DEBUG("Examine failed"); + LOG_DEBUG("Examine %s failed", "CPUID"); return retval; } if ((retval = mem_ap_read_atomic_u32(swjdp, armv7a->debug_base + CPUDBG_CTYPR, &ctypr)) != ERROR_OK) { - LOG_DEBUG("Examine failed"); + LOG_DEBUG("Examine %s failed", "CTYPR"); return retval; } if ((retval = mem_ap_read_atomic_u32(swjdp, armv7a->debug_base + CPUDBG_TTYPR, &ttypr)) != ERROR_OK) { - LOG_DEBUG("Examine failed"); + LOG_DEBUG("Examine %s failed", "TTYPR"); return retval; } if ((retval = mem_ap_read_atomic_u32(swjdp, armv7a->debug_base + CPUDBG_DIDR, &didr)) != ERROR_OK) { - LOG_DEBUG("Examine failed"); + LOG_DEBUG("Examine %s failed", "DIDR"); return retval; } @@ -1465,20 +1526,7 @@ static int cortex_a8_examine_first(struct target *target) cortex_a8->brp_list[i].BRPn = i; } - /* Setup Watchpoint Register Pairs */ - cortex_a8->wrp_num = ((didr >> 28) & 0x0F) + 1; - cortex_a8->wrp_num_available = cortex_a8->wrp_num; - cortex_a8->wrp_list = calloc(cortex_a8->wrp_num, sizeof(struct cortex_a8_wrp)); - for (i = 0; i < cortex_a8->wrp_num; i++) - { - cortex_a8->wrp_list[i].used = 0; - cortex_a8->wrp_list[i].type = 0; - cortex_a8->wrp_list[i].value = 0; - cortex_a8->wrp_list[i].control = 0; - cortex_a8->wrp_list[i].WRPn = i; - } - LOG_DEBUG("Configured %i hw breakpoint pairs and %i hw watchpoint pairs", - cortex_a8->brp_num , cortex_a8->wrp_num); + LOG_DEBUG("Configured %i hw breakpoints", cortex_a8->brp_num); target_set_examined(target); return ERROR_OK; @@ -1556,7 +1604,7 @@ static int cortex_a8_init_arch_info(struct target *target, // arm7_9->handle_target_request = cortex_a8_handle_target_request; /* REVISIT v7a setup should be in a v7a-specific routine */ - armv4_5_init_arch_info(target, armv4_5); + arm_init_arch_info(target, armv4_5); armv7a->common_magic = ARMV7_COMMON_MAGIC; target_register_timer_callback(cortex_a8_handle_target_request, 1, 1, target); @@ -1595,13 +1643,13 @@ COMMAND_HANDLER(cortex_a8_handle_dbginit_command) static const struct command_registration cortex_a8_exec_command_handlers[] = { { .name = "cache_info", - .handler = &cortex_a8_handle_cache_info_command, + .handler = cortex_a8_handle_cache_info_command, .mode = COMMAND_EXEC, .help = "display information about target caches", }, { .name = "dbginit", - .handler = &cortex_a8_handle_dbginit_command, + .handler = cortex_a8_handle_dbginit_command, .mode = COMMAND_EXEC, .help = "Initialize core debug", }, @@ -1639,7 +1687,8 @@ struct target_type cortexa8_target = { .deassert_reset = cortex_a8_deassert_reset, .soft_reset_halt = NULL, - .get_gdb_reg_list = armv4_5_get_gdb_reg_list, + /* REVISIT allow exporting VFP3 registers ... */ + .get_gdb_reg_list = arm_get_gdb_reg_list, .read_memory = cortex_a8_read_memory, .write_memory = cortex_a8_write_memory,