X-Git-Url: https://review.openocd.org/gitweb?a=blobdiff_plain;f=src%2Ftarget%2Fcortex_a8.c;h=b006e81a64df7f91547fce2a4020b70d2042c083;hb=bf3abc48f008e0a0c0e42b943481872599463af6;hp=c6a46c50ce1ce7f1da46c48a14251ac163201927;hpb=69c751956293e822faa6cf844f2864d81c36a578;p=openocd.git

diff --git a/src/target/cortex_a8.c b/src/target/cortex_a8.c
index c6a46c50ce..b006e81a64 100644
--- a/src/target/cortex_a8.c
+++ b/src/target/cortex_a8.c
@@ -457,7 +457,7 @@ static int cortex_a8_resume(struct target *target, int current,
 		uint32_t address, int handle_breakpoints, int debug_execution)
 {
 	struct armv7a_common *armv7a = target_to_armv7a(target);
-	struct armv4_5_common_s *armv4_5 = &armv7a->armv4_5_common;
+	struct arm *armv4_5 = &armv7a->armv4_5_common;
 	struct swjdp_common *swjdp = &armv7a->swjdp_info;
 
 //	struct breakpoint *breakpoint = NULL;
@@ -496,8 +496,7 @@ static int cortex_a8_resume(struct target *target, int current,
 
 	/* current = 1: continue on current pc, otherwise continue at <address> */
 	resume_pc = buf_get_u32(
-			ARMV4_5_CORE_REG_MODE(armv4_5->core_cache,
-				armv4_5->core_mode, 15).value,
+			armv4_5->core_cache->reg_list[15].value,
 			0, 32);
 	if (!current)
 		resume_pc = address;
@@ -522,13 +521,10 @@ static int cortex_a8_resume(struct target *target, int current,
 		return ERROR_FAIL;
 	}
 	LOG_DEBUG("resume pc = 0x%08" PRIx32, resume_pc);
-	buf_set_u32(ARMV4_5_CORE_REG_MODE(armv4_5->core_cache,
-				armv4_5->core_mode, 15).value,
+	buf_set_u32(armv4_5->core_cache->reg_list[15].value,
 			0, 32, resume_pc);
-	ARMV4_5_CORE_REG_MODE(armv4_5->core_cache,
-			armv4_5->core_mode, 15).dirty = 1;
-	ARMV4_5_CORE_REG_MODE(armv4_5->core_cache,
-			armv4_5->core_mode, 15).valid = 1;
+	armv4_5->core_cache->reg_list[15].dirty = 1;
+	armv4_5->core_cache->reg_list[15].valid = 1;
 
 	cortex_a8_restore_context(target);
 
@@ -587,7 +583,7 @@ static int cortex_a8_debug_entry(struct target *target)
 	struct working_area *regfile_working_area = NULL;
 	struct cortex_a8_common *cortex_a8 = target_to_cortex_a8(target);
 	struct armv7a_common *armv7a = target_to_armv7a(target);
-	struct armv4_5_common_s *armv4_5 = &armv7a->armv4_5_common;
+	struct arm *armv4_5 = &armv7a->armv4_5_common;
 	struct swjdp_common *swjdp = &armv7a->swjdp_info;
 	struct reg *reg;
 
@@ -648,41 +644,12 @@ static int cortex_a8_debug_entry(struct target *target)
 	dap_ap_select(swjdp, swjdp_debugap);
 	LOG_DEBUG("cpsr: %8.8" PRIx32, cpsr);
 
-	armv4_5->core_mode = cpsr & 0x1F;
-
-	i = (cpsr >> 5) & 1;	/* T */
-	i |= (cpsr >> 23) & 1;	/* J << 1 */
-	switch (i) {
-	case 0:	/* J = 0, T = 0 */
-		armv4_5->core_state = ARMV4_5_STATE_ARM;
-		break;
-	case 1:	/* J = 0, T = 1 */
-		armv4_5->core_state = ARMV4_5_STATE_THUMB;
-		break;
-	case 2:	/* J = 1, T = 0 */
-		LOG_WARNING("Jazelle state -- not handled");
-		armv4_5->core_state = ARMV4_5_STATE_JAZELLE;
-		break;
-	case 3:	/* J = 1, T = 1 */
-		/* ThumbEE is very much like Thumb, but some of the
-		 * instructions are different.  Single stepping and
-		 * breakpoints need updating...
-		 */
-		LOG_WARNING("ThumbEE -- incomplete support");
-		armv4_5->core_state = ARM_STATE_THUMB_EE;
-		break;
-	}
+	arm_set_cpsr(armv4_5, cpsr);
 
 	/* update cache */
-	reg = armv4_5->core_cache->reg_list + ARMV4_5_CPSR;
-	buf_set_u32(reg->value, 0, 32, cpsr);
-	reg->valid = 1;
-	reg->dirty = 0;
-
 	for (i = 0; i <= ARM_PC; i++)
 	{
-		reg = &ARMV4_5_CORE_REG_MODE(armv4_5->core_cache,
-					armv4_5->core_mode, i);
+		reg = arm_reg_current(armv4_5, i);
 
 		buf_set_u32(reg->value, 0, 32, regfile[i]);
 		reg->valid = 1;
@@ -700,13 +667,10 @@ static int cortex_a8_debug_entry(struct target *target)
 		// ARM state
 		regfile[ARM_PC] -= 8;
 	}
-	buf_set_u32(ARMV4_5_CORE_REG_MODE(armv4_5->core_cache,
-				armv4_5->core_mode, ARM_PC).value,
-			0, 32, regfile[ARM_PC]);
 
-	ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 0)
-		.dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache,
-				armv4_5->core_mode, 0).valid;
+	reg = armv4_5->core_cache->reg_list + 15;
+	buf_set_u32(reg->value, 0, 32, regfile[ARM_PC]);
+	reg->dirty = reg->valid;
 	ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 15)
 		.dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache,
 				armv4_5->core_mode, 15).valid;
@@ -771,7 +735,7 @@ static int cortex_a8_step(struct target *target, int current, uint32_t address,
 		int handle_breakpoints)
 {
 	struct armv7a_common *armv7a = target_to_armv7a(target);
-	struct armv4_5_common_s *armv4_5 = &armv7a->armv4_5_common;
+	struct arm *armv4_5 = &armv7a->armv4_5_common;
 	struct breakpoint *breakpoint = NULL;
 	struct breakpoint stepbreakpoint;
 
@@ -879,7 +843,7 @@ static int cortex_a8_restore_context(struct target *target)
 		for (i = max - 1, r = cache->reg_list + 1; i > 0; i--, r++) {
 			struct arm_reg *reg;
 
-			if (!r->dirty || i == ARMV4_5_CPSR)
+			if (!r->dirty || r == armv7a->armv4_5_common.cpsr)
 				continue;
 			reg = r->arch_info;
 
@@ -915,7 +879,7 @@ static int cortex_a8_restore_context(struct target *target)
 	} while (flushed);
 
 	/* now flush CPSR if needed ... */
-	r = cache->reg_list + ARMV4_5_CPSR;
+	r = armv7a->armv4_5_common.cpsr;
 	if (flush_cpsr || r->dirty) {
 		value = buf_get_u32(r->value, 0, 32);
 		cortex_a8_dap_write_coreregister_u32(target, value, 16);
@@ -943,7 +907,7 @@ static int cortex_a8_load_core_reg_u32(struct target *target, int num,
 		armv4_5_mode_t mode, uint32_t * value)
 {
 	int retval;
-	struct armv4_5_common_s *armv4_5 = target_to_armv4_5(target);
+	struct arm *armv4_5 = target_to_armv4_5(target);
 
 	if ((num <= ARM_CPSR))
 	{
@@ -981,7 +945,7 @@ static int cortex_a8_store_core_reg_u32(struct target *target, int num,
 {
 	int retval;
 //	uint32_t reg;
-	struct armv4_5_common_s *armv4_5 = target_to_armv4_5(target);
+	struct arm *armv4_5 = target_to_armv4_5(target);
 
 #ifdef ARMV7_GDB_HACKS
 	/* If the LR register is being modified, make sure it will put us
@@ -1026,8 +990,7 @@ static int cortex_a8_read_core_reg(struct target *target, struct reg *r,
 {
 	uint32_t value;
 	int retval;
-	struct armv4_5_common_s *armv4_5 = target_to_armv4_5(target);
-	struct reg_cache *cache = armv4_5->core_cache;
+	struct arm *armv4_5 = target_to_armv4_5(target);
 	struct reg *cpsr_r = NULL;
 	uint32_t cpsr = 0;
 	unsigned cookie = num;
@@ -1043,7 +1006,7 @@ static int cortex_a8_read_core_reg(struct target *target, struct reg *r,
 			mode = ARMV4_5_MODE_ANY;
 
 		if (mode != ARMV4_5_MODE_ANY) {
-			cpsr_r = cache->reg_list + ARMV4_5_CPSR;
+			cpsr_r = armv4_5->cpsr;
 			cpsr = buf_get_u32(cpsr_r->value, 0, 32);
 			cortex_a8_write_core_reg(target, cpsr_r,
 					16, ARMV4_5_MODE_ANY, mode);
@@ -1082,8 +1045,7 @@ static int cortex_a8_write_core_reg(struct target *target, struct reg *r,
 		int num, enum armv4_5_mode mode, uint32_t value)
 {
 	int retval;
-	struct armv4_5_common_s *armv4_5 = target_to_armv4_5(target);
-	struct reg_cache *cache = armv4_5->core_cache;
+	struct arm *armv4_5 = target_to_armv4_5(target);
 	struct reg *cpsr_r = NULL;
 	uint32_t cpsr = 0;
 	unsigned cookie = num;
@@ -1099,7 +1061,7 @@ static int cortex_a8_write_core_reg(struct target *target, struct reg *r,
 			mode = ARMV4_5_MODE_ANY;
 
 		if (mode != ARMV4_5_MODE_ANY) {
-			cpsr_r = cache->reg_list + ARMV4_5_CPSR;
+			cpsr_r = armv4_5->cpsr;
 			cpsr = buf_get_u32(cpsr_r->value, 0, 32);
 			cortex_a8_write_core_reg(target, cpsr_r,
 					16, ARMV4_5_MODE_ANY, mode);
@@ -1614,7 +1576,7 @@ static int cortex_a8_examine(struct target *target)
 static void cortex_a8_build_reg_cache(struct target *target)
 {
 	struct reg_cache **cache_p = register_get_last_cache_p(&target->reg_cache);
-	struct armv4_5_common_s *armv4_5 = target_to_armv4_5(target);
+	struct arm *armv4_5 = target_to_armv4_5(target);
 
 	armv4_5->core_type = ARM_MODE_MON;