X-Git-Url: https://review.openocd.org/gitweb?a=blobdiff_plain;f=src%2Ftarget%2Fcortex_a8.c;h=a2f3ea060bb710143fd915d69acd2044fa27b075;hb=221ce7c89b2c8792be4099687ed23f04f4e5018d;hp=cfec48b6519827c2bc8b8940f4af4d82ba269f2d;hpb=2a25c968bf4ffec39ee76da0a164e46bd4215134;p=openocd.git diff --git a/src/target/cortex_a8.c b/src/target/cortex_a8.c index cfec48b651..a2f3ea060b 100644 --- a/src/target/cortex_a8.c +++ b/src/target/cortex_a8.c @@ -11,6 +11,9 @@ * Copyright (C) 2009 by Dirk Behme * * dirk.behme@gmail.com - copy from cortex_m3 * * * + * Copyright (C) 2010 Øyvind Harboe * + * oyvind.harboe@zylin.com * + * * * This program is free software; you can redistribute it and/or modify * * it under the terms of the GNU General Public License as published by * * the Free Software Foundation; either version 2 of the License, or * @@ -39,6 +42,7 @@ #include "target_request.h" #include "target_type.h" #include "arm_opcodes.h" +#include static int cortex_a8_poll(struct target *target); static int cortex_a8_debug_entry(struct target *target); @@ -88,16 +92,28 @@ static int cortex_a8_init_debug_access(struct target *target) /* The debugport might be uninitialised so try twice */ retval = mem_ap_write_atomic_u32(swjdp, armv7a->debug_base + CPUDBG_LOCKACCESS, 0xC5ACCE55); if (retval != ERROR_OK) - mem_ap_write_atomic_u32(swjdp, armv7a->debug_base + CPUDBG_LOCKACCESS, 0xC5ACCE55); + { + /* try again */ + retval = mem_ap_write_atomic_u32(swjdp, armv7a->debug_base + CPUDBG_LOCKACCESS, 0xC5ACCE55); + if (retval == ERROR_OK) + { + LOG_USER("Locking debug access failed on first, but succeeded on second try."); + } + } + if (retval != ERROR_OK) + return retval; /* Clear Sticky Power Down status Bit in PRSR to enable access to the registers in the Core Power Domain */ retval = mem_ap_read_atomic_u32(swjdp, armv7a->debug_base + CPUDBG_PRSR, &dummy); + if (retval != ERROR_OK) + return retval; + /* Enabling of instruction execution in debug mode is done in debug_entry code */ /* Resync breakpoint registers */ - /* Since this is likley called from init or reset, update targtet state information*/ - cortex_a8_poll(target); + /* Since this is likely called from init or reset, update target state information*/ + retval = cortex_a8_poll(target); return retval; } @@ -131,7 +147,9 @@ static int cortex_a8_exec_opcode(struct target *target, } } - mem_ap_write_u32(swjdp, armv7a->debug_base + CPUDBG_ITR, opcode); + retval = mem_ap_write_u32(swjdp, armv7a->debug_base + CPUDBG_ITR, opcode); + if (retval != ERROR_OK) + return retval; do { @@ -162,11 +180,20 @@ static int cortex_a8_read_regs_through_mem(struct target *target, uint32_t addre struct armv7a_common *armv7a = target_to_armv7a(target); struct adiv5_dap *swjdp = &armv7a->dap; - cortex_a8_dap_read_coreregister_u32(target, regfile, 0); - cortex_a8_dap_write_coreregister_u32(target, address, 0); - cortex_a8_exec_opcode(target, ARMV4_5_STMIA(0, 0xFFFE, 0, 0), NULL); + retval = cortex_a8_dap_read_coreregister_u32(target, regfile, 0); + if (retval != ERROR_OK) + return retval; + retval = cortex_a8_dap_write_coreregister_u32(target, address, 0); + if (retval != ERROR_OK) + return retval; + retval = cortex_a8_exec_opcode(target, ARMV4_5_STMIA(0, 0xFFFE, 0, 0), NULL); + if (retval != ERROR_OK) + return retval; + dap_ap_select(swjdp, swjdp_memoryap); - mem_ap_read_buf_u32(swjdp, (uint8_t *)(®file[1]), 4*15, address); + retval = mem_ap_read_buf_u32(swjdp, (uint8_t *)(®file[1]), 4*15, address); + if (retval != ERROR_OK) + return retval; dap_ap_select(swjdp, swjdp_debugap); return retval; @@ -187,27 +214,37 @@ static int cortex_a8_dap_read_coreregister_u32(struct target *target, if (reg < 15) { /* Rn to DCCTX, "MCR p14, 0, Rn, c0, c5, 0" 0xEE00nE15 */ - cortex_a8_exec_opcode(target, + retval = cortex_a8_exec_opcode(target, ARMV4_5_MCR(14, 0, reg, 0, 5, 0), &dscr); + if (retval != ERROR_OK) + return retval; } else if (reg == 15) { /* "MOV r0, r15"; then move r0 to DCCTX */ - cortex_a8_exec_opcode(target, 0xE1A0000F, &dscr); - cortex_a8_exec_opcode(target, + retval = cortex_a8_exec_opcode(target, 0xE1A0000F, &dscr); + if (retval != ERROR_OK) + return retval; + retval = cortex_a8_exec_opcode(target, ARMV4_5_MCR(14, 0, 0, 0, 5, 0), &dscr); + if (retval != ERROR_OK) + return retval; } else { /* "MRS r0, CPSR" or "MRS r0, SPSR" * then move r0 to DCCTX */ - cortex_a8_exec_opcode(target, ARMV4_5_MRS(0, reg & 1), &dscr); - cortex_a8_exec_opcode(target, + retval = cortex_a8_exec_opcode(target, ARMV4_5_MRS(0, reg & 1), &dscr); + if (retval != ERROR_OK) + return retval; + retval = cortex_a8_exec_opcode(target, ARMV4_5_MCR(14, 0, 0, 0, 5, 0), &dscr); + if (retval != ERROR_OK) + return retval; } /* Wait for DTRRXfull then read DTRRTX */ @@ -215,6 +252,8 @@ static int cortex_a8_dap_read_coreregister_u32(struct target *target, { retval = mem_ap_read_atomic_u32(swjdp, armv7a->debug_base + CPUDBG_DSCR, &dscr); + if (retval != ERROR_OK) + return retval; } retval = mem_ap_read_atomic_u32(swjdp, @@ -238,12 +277,16 @@ static int cortex_a8_dap_write_coreregister_u32(struct target *target, /* Check that DCCRX is not full */ retval = mem_ap_read_atomic_u32(swjdp, armv7a->debug_base + CPUDBG_DSCR, &dscr); + if (retval != ERROR_OK) + return retval; if (dscr & DSCR_DTR_RX_FULL) { LOG_ERROR("DSCR_DTR_RX_FULL, dscr 0x%08" PRIx32, dscr); /* Clear DCCRX with MCR(p14, 0, Rd, c0, c5, 0), opcode 0xEE000E15 */ - cortex_a8_exec_opcode(target, ARMV4_5_MRC(14, 0, 0, 0, 5, 0), + retval = cortex_a8_exec_opcode(target, ARMV4_5_MRC(14, 0, 0, 0, 5, 0), &dscr); + if (retval != ERROR_OK) + return retval; } if (Rd > 17) @@ -253,37 +296,53 @@ static int cortex_a8_dap_write_coreregister_u32(struct target *target, LOG_DEBUG("write DCC 0x%08" PRIx32, value); retval = mem_ap_write_u32(swjdp, armv7a->debug_base + CPUDBG_DTRRX, value); + if (retval != ERROR_OK) + return retval; if (Rd < 15) { /* DCCRX to Rn, "MCR p14, 0, Rn, c0, c5, 0", 0xEE00nE15 */ - cortex_a8_exec_opcode(target, ARMV4_5_MRC(14, 0, Rd, 0, 5, 0), + retval = cortex_a8_exec_opcode(target, ARMV4_5_MRC(14, 0, Rd, 0, 5, 0), &dscr); + if (retval != ERROR_OK) + return retval; } else if (Rd == 15) { /* DCCRX to R0, "MCR p14, 0, R0, c0, c5, 0", 0xEE000E15 * then "mov r15, r0" */ - cortex_a8_exec_opcode(target, ARMV4_5_MRC(14, 0, 0, 0, 5, 0), + retval = cortex_a8_exec_opcode(target, ARMV4_5_MRC(14, 0, 0, 0, 5, 0), &dscr); - cortex_a8_exec_opcode(target, 0xE1A0F000, &dscr); + if (retval != ERROR_OK) + return retval; + retval = cortex_a8_exec_opcode(target, 0xE1A0F000, &dscr); + if (retval != ERROR_OK) + return retval; } else { /* DCCRX to R0, "MCR p14, 0, R0, c0, c5, 0", 0xEE000E15 * then "MSR CPSR_cxsf, r0" or "MSR SPSR_cxsf, r0" (all fields) */ - cortex_a8_exec_opcode(target, ARMV4_5_MRC(14, 0, 0, 0, 5, 0), + retval = cortex_a8_exec_opcode(target, ARMV4_5_MRC(14, 0, 0, 0, 5, 0), &dscr); - cortex_a8_exec_opcode(target, ARMV4_5_MSR_GP(0, 0xF, Rd & 1), + if (retval != ERROR_OK) + return retval; + retval = cortex_a8_exec_opcode(target, ARMV4_5_MSR_GP(0, 0xF, Rd & 1), &dscr); + if (retval != ERROR_OK) + return retval; /* "Prefetch flush" after modifying execution status in CPSR */ if (Rd == 16) - cortex_a8_exec_opcode(target, + { + retval = cortex_a8_exec_opcode(target, ARMV4_5_MCR(15, 0, 0, 7, 5, 4), &dscr); + if (retval != ERROR_OK) + return retval; + } } return retval; @@ -339,10 +398,14 @@ static int cortex_a8_read_dcc(struct cortex_a8_common *a8, uint32_t *data, retval = mem_ap_read_atomic_u32(swjdp, a8->armv7a_common.debug_base + CPUDBG_DSCR, &dscr); + if (retval != ERROR_OK) + return retval; } retval = mem_ap_read_atomic_u32(swjdp, a8->armv7a_common.debug_base + CPUDBG_DTRTX, data); + if (retval != ERROR_OK) + return retval; //LOG_DEBUG("read DCC 0x%08" PRIx32, *data); if (dscr_p) @@ -359,11 +422,22 @@ static int cortex_a8_dpm_prepare(struct arm_dpm *dpm) int retval; /* set up invariant: INSTR_COMP is set after ever DPM operation */ - do { + long long then = timeval_ms(); + for (;;) + { retval = mem_ap_read_atomic_u32(swjdp, a8->armv7a_common.debug_base + CPUDBG_DSCR, &dscr); - } while ((dscr & DSCR_INSTR_COMP) == 0); + if (retval != ERROR_OK) + return retval; + if ((dscr & DSCR_INSTR_COMP) != 0) + break; + if (timeval_ms() > then + 1000) + { + LOG_ERROR("Timeout waiting for dpm prepare"); + return ERROR_FAIL; + } + } /* this "should never happen" ... */ if (dscr & DSCR_DTR_RX_FULL) { @@ -373,6 +447,8 @@ static int cortex_a8_dpm_prepare(struct arm_dpm *dpm) a8->armv7a_common.armv4_5_common.target, ARMV4_5_MRC(14, 0, 0, 0, 5, 0), &dscr); + if (retval != ERROR_OK) + return retval; } return retval; @@ -413,6 +489,8 @@ static int cortex_a8_instr_write_data_r0(struct arm_dpm *dpm, a8->armv7a_common.armv4_5_common.target, ARMV4_5_MRC(14, 0, 0, 0, 5, 0), &dscr); + if (retval != ERROR_OK) + return retval; /* then the opcode, taking data from R0 */ retval = cortex_a8_exec_opcode( @@ -446,6 +524,8 @@ static int cortex_a8_instr_read_data_dcc(struct arm_dpm *dpm, a8->armv7a_common.armv4_5_common.target, opcode, &dscr); + if (retval != ERROR_OK) + return retval; return cortex_a8_read_dcc(a8, data, &dscr); } @@ -463,12 +543,16 @@ static int cortex_a8_instr_read_data_r0(struct arm_dpm *dpm, a8->armv7a_common.armv4_5_common.target, opcode, &dscr); + if (retval != ERROR_OK) + return retval; /* write R0 to DCC */ retval = cortex_a8_exec_opcode( a8->armv7a_common.armv4_5_common.target, ARMV4_5_MCR(14, 0, 0, 0, 5, 0), &dscr); + if (retval != ERROR_OK) + return retval; return cortex_a8_read_dcc(a8, data, &dscr); } @@ -646,21 +730,38 @@ static int cortex_a8_halt(struct target *target) */ retval = mem_ap_write_atomic_u32(swjdp, armv7a->debug_base + CPUDBG_DRCR, 0x1); + if (retval != ERROR_OK) + goto out; /* * enter halting debug mode */ - mem_ap_read_atomic_u32(swjdp, armv7a->debug_base + CPUDBG_DSCR, &dscr); + retval = mem_ap_read_atomic_u32(swjdp, armv7a->debug_base + CPUDBG_DSCR, &dscr); + if (retval != ERROR_OK) + goto out; + retval = mem_ap_write_atomic_u32(swjdp, armv7a->debug_base + CPUDBG_DSCR, dscr | DSCR_HALT_DBG_MODE); - if (retval != ERROR_OK) goto out; - do { - mem_ap_read_atomic_u32(swjdp, + long long then = timeval_ms(); + for (;;) + { + retval = mem_ap_read_atomic_u32(swjdp, armv7a->debug_base + CPUDBG_DSCR, &dscr); - } while ((dscr & DSCR_CORE_HALTED) == 0); + if (retval != ERROR_OK) + goto out; + if ((dscr & DSCR_CORE_HALTED) != 0) + { + break; + } + if (timeval_ms() > then + 1000) + { + LOG_ERROR("Timeout waiting for halt"); + return ERROR_FAIL; + } + } target->debug_reason = DBG_REASON_DBGRQ; @@ -675,6 +776,7 @@ static int cortex_a8_resume(struct target *target, int current, struct armv7a_common *armv7a = target_to_armv7a(target); struct arm *armv4_5 = &armv7a->armv4_5_common; struct adiv5_dap *swjdp = &armv7a->dap; + int retval; // struct breakpoint *breakpoint = NULL; uint32_t resume_pc, dscr; @@ -758,12 +860,25 @@ static int cortex_a8_resume(struct target *target, int current, * REVISIT: for single stepping, we probably want to * disable IRQs by default, with optional override... */ - mem_ap_write_atomic_u32(swjdp, armv7a->debug_base + CPUDBG_DRCR, 0x2); + retval = mem_ap_write_atomic_u32(swjdp, armv7a->debug_base + CPUDBG_DRCR, 0x2); + if (retval != ERROR_OK) + return retval; - do { - mem_ap_read_atomic_u32(swjdp, + long long then = timeval_ms(); + for (;;) + { + retval = mem_ap_read_atomic_u32(swjdp, armv7a->debug_base + CPUDBG_DSCR, &dscr); - } while ((dscr & DSCR_CORE_RESTARTED) == 0); + if (retval != ERROR_OK) + return retval; + if ((dscr & DSCR_CORE_RESTARTED) != 0) + break; + if (timeval_ms() > then + 1000) + { + LOG_ERROR("Timeout waiting for resume"); + return ERROR_FAIL; + } + } target->debug_reason = DBG_REASON_NOTHALTED; target->state = TARGET_RUNNING; @@ -804,8 +919,10 @@ static int cortex_a8_debug_entry(struct target *target) LOG_DEBUG("dscr = 0x%08" PRIx32, cortex_a8->cpudbg_dscr); /* REVISIT surely we should not re-read DSCR !! */ - mem_ap_read_atomic_u32(swjdp, + retval = mem_ap_read_atomic_u32(swjdp, armv7a->debug_base + CPUDBG_DSCR, &dscr); + if (retval != ERROR_OK) + return retval; /* REVISIT see A8 TRM 12.11.4 steps 2..3 -- make sure that any * imprecise data aborts get discarded by issuing a Data @@ -816,6 +933,8 @@ static int cortex_a8_debug_entry(struct target *target) dscr |= DSCR_ITR_EN; retval = mem_ap_write_atomic_u32(swjdp, armv7a->debug_base + CPUDBG_DSCR, dscr); + if (retval != ERROR_OK) + return retval; /* Examine debug reason */ arm_dpm_report_dscr(&armv7a->dpm, cortex_a8->cpudbg_dscr); @@ -827,6 +946,8 @@ static int cortex_a8_debug_entry(struct target *target) retval = mem_ap_read_atomic_u32(swjdp, armv7a->debug_base + CPUDBG_WFAR, &wfar); + if (retval != ERROR_OK) + return retval; arm_dpm_report_wfar(&armv7a->dpm, wfar); } @@ -850,7 +971,9 @@ static int cortex_a8_debug_entry(struct target *target) target_free_working_area(target, regfile_working_area); /* read Current PSR */ - cortex_a8_dap_read_coreregister_u32(target, &cpsr, 16); + retval = cortex_a8_dap_read_coreregister_u32(target, &cpsr, 16); + if (retval != ERROR_OK) + return retval; dap_ap_select(swjdp, swjdp_debugap); LOG_DEBUG("cpsr: %8.8" PRIx32, cpsr); @@ -951,6 +1074,7 @@ static int cortex_a8_step(struct target *target, int current, uint32_t address, struct breakpoint *breakpoint = NULL; struct breakpoint stepbreakpoint; struct reg *r; + int retval; int timeout = 100; @@ -994,15 +1118,19 @@ static int cortex_a8_step(struct target *target, int current, uint32_t address, target->debug_reason = DBG_REASON_SINGLESTEP; - cortex_a8_resume(target, 1, address, 0, 0); + retval = cortex_a8_resume(target, 1, address, 0, 0); + if (retval != ERROR_OK) + return retval; while (target->state != TARGET_HALTED) { - cortex_a8_poll(target); + retval = cortex_a8_poll(target); + if (retval != ERROR_OK) + return retval; if (--timeout == 0) { - LOG_WARNING("timeout waiting for target halt"); - break; + LOG_ERROR("timeout waiting for target halt"); + return ERROR_FAIL; } } @@ -1035,7 +1163,7 @@ static int cortex_a8_restore_context(struct target *target, bool bpwp) /* - * Cortex-A8 Breakpoint and watchpoint fuctions + * Cortex-A8 Breakpoint and watchpoint functions */ /* Setup hardware Breakpoint Register Pair */ @@ -1195,7 +1323,7 @@ static int cortex_a8_remove_breakpoint(struct target *target, struct breakpoint struct cortex_a8_common *cortex_a8 = target_to_cortex_a8(target); #if 0 -/* It is perfectly possible to remove brakpoints while the taget is running */ +/* It is perfectly possible to remove breakpoints while the target is running */ if (target->state != TARGET_HALTED) { LOG_WARNING("target not halted"); @@ -1217,7 +1345,7 @@ static int cortex_a8_remove_breakpoint(struct target *target, struct breakpoint /* - * Cortex-A8 Reset fuctions + * Cortex-A8 Reset functions */ static int cortex_a8_assert_reset(struct target *target) @@ -1259,6 +1387,8 @@ static int cortex_a8_deassert_reset(struct target *target) jtag_add_reset(0, 0); retval = cortex_a8_poll(target); + if (retval != ERROR_OK) + return retval; if (target->reset_halt) { if (target->state != TARGET_HALTED) { @@ -1313,12 +1443,16 @@ static int cortex_a8_read_memory(struct target *target, uint32_t address, { int enabled = 0; uint32_t virt, phys; + int retval; /* cortex_a8 handles unaligned memory access */ // ??? dap_ap_select(swjdp, swjdp_memoryap); LOG_DEBUG("Reading memory at address 0x%x; size %d; count %d", address, size, count); - cortex_a8_mmu(target, &enabled); + retval = cortex_a8_mmu(target, &enabled); + if (retval != ERROR_OK) + return retval; + if(enabled) { virt = address; @@ -1416,11 +1550,14 @@ static int cortex_a8_write_memory(struct target *target, uint32_t address, { int enabled = 0; uint32_t virt, phys; + int retval; // ??? dap_ap_select(swjdp, swjdp_memoryap); LOG_DEBUG("Writing memory to address 0x%x; size %d; count %d", address, size, count); - cortex_a8_mmu(target, &enabled); + retval = cortex_a8_mmu(target, &enabled); + if (retval != ERROR_OK) + return retval; if(enabled) { virt = address; @@ -1523,8 +1660,14 @@ static int cortex_a8_examine_first(struct target *target) /* We do one extra read to ensure DAP is configured, * we call ahbap_debugport_init(swjdp) instead */ - ahbap_debugport_init(swjdp); - mem_ap_read_atomic_u32(swjdp, armv7a->debug_base + CPUDBG_CPUID, &cpuid); + retval = ahbap_debugport_init(swjdp); + if (retval != ERROR_OK) + return retval; + + retval = mem_ap_read_atomic_u32(swjdp, armv7a->debug_base + CPUDBG_CPUID, &cpuid); + if (retval != ERROR_OK) + return retval; + if ((retval = mem_ap_read_atomic_u32(swjdp, armv7a->debug_base + CPUDBG_CPUID, &cpuid)) != ERROR_OK) { @@ -1559,7 +1702,9 @@ static int cortex_a8_examine_first(struct target *target) LOG_DEBUG("didr = 0x%08" PRIx32, didr); armv7a->armv4_5_common.core_type = ARM_MODE_MON; - cortex_a8_dpm_setup(cortex_a8, didr); + retval = cortex_a8_dpm_setup(cortex_a8, didr); + if (retval != ERROR_OK) + return retval; /* Setup Breakpoint Register Pairs */ cortex_a8->brp_num = ((didr >> 24) & 0x0F) + 1; @@ -1720,7 +1865,7 @@ static uint32_t cortex_a8_get_ttb(struct target *target) 2, 0, /* CRn, CRm */ &ttb); } - /* finaly we don't know whose ttb to use: user or kernel */ + /* finally we don't know whose ttb to use: user or kernel */ else LOG_ERROR("Don't know how to get ttb for current mode!!!");