X-Git-Url: https://review.openocd.org/gitweb?a=blobdiff_plain;f=src%2Ftarget%2Fcortex_a8.c;h=28c75b591da3f6dc4b9f2dd24bc3843cb8dd3bae;hb=c008d30fe85a674842632e32d732e22e0a91b95d;hp=29fffaebb2154944e2225ea4dccb3c000731ff56;hpb=1ebdc244941c02503fc042e538991d617157184f;p=openocd.git diff --git a/src/target/cortex_a8.c b/src/target/cortex_a8.c index 29fffaebb2..28c75b591d 100644 --- a/src/target/cortex_a8.c +++ b/src/target/cortex_a8.c @@ -33,88 +33,23 @@ #include "config.h" #endif +#include "breakpoints.h" #include "cortex_a8.h" -#include "armv7a.h" -#include "armv4_5.h" - +#include "register.h" #include "target_request.h" #include "target_type.h" -/* cli handling */ -int cortex_a8_register_commands(struct command_context_s *cmd_ctx); - -/* forward declarations */ -int cortex_a8_target_create(struct target_s *target, Jim_Interp *interp); -int cortex_a8_init_target(struct command_context_s *cmd_ctx, - struct target_s *target); -int cortex_a8_examine(struct target_s *target); -int cortex_a8_poll(target_t *target); -int cortex_a8_halt(target_t *target); -int cortex_a8_resume(struct target_s *target, int current, uint32_t address, - int handle_breakpoints, int debug_execution); -int cortex_a8_step(struct target_s *target, int current, uint32_t address, - int handle_breakpoints); -int cortex_a8_debug_entry(target_t *target); -int cortex_a8_restore_context(target_t *target); -int cortex_a8_bulk_write_memory(target_t *target, uint32_t address, - uint32_t count, uint8_t *buffer); -int cortex_a8_set_breakpoint(struct target_s *target, - breakpoint_t *breakpoint, uint8_t matchmode); -int cortex_a8_unset_breakpoint(struct target_s *target, breakpoint_t *breakpoint); -int cortex_a8_add_breakpoint(struct target_s *target, breakpoint_t *breakpoint); -int cortex_a8_remove_breakpoint(struct target_s *target, breakpoint_t *breakpoint); -int cortex_a8_dap_read_coreregister_u32(target_t *target, +static int cortex_a8_poll(struct target *target); +static int cortex_a8_debug_entry(struct target *target); +static int cortex_a8_restore_context(struct target *target); +static int cortex_a8_set_breakpoint(struct target *target, + struct breakpoint *breakpoint, uint8_t matchmode); +static int cortex_a8_unset_breakpoint(struct target *target, + struct breakpoint *breakpoint); +static int cortex_a8_dap_read_coreregister_u32(struct target *target, uint32_t *value, int regnum); -int cortex_a8_dap_write_coreregister_u32(target_t *target, +static int cortex_a8_dap_write_coreregister_u32(struct target *target, uint32_t value, int regnum); -int cortex_a8_assert_reset(target_t *target); -int cortex_a8_deassert_reset(target_t *target); - -static int cortex_a8_mrc(target_t *target, int cpnum, uint32_t op1, - uint32_t op2, uint32_t CRn, uint32_t CRm, uint32_t *value); -static int cortex_a8_mcr(target_t *target, int cpnum, uint32_t op1, - uint32_t op2, uint32_t CRn, uint32_t CRm, uint32_t value); - -target_type_t cortexa8_target = -{ - .name = "cortex_a8", - - .poll = cortex_a8_poll, - .arch_state = armv7a_arch_state, - - .target_request_data = NULL, - - .halt = cortex_a8_halt, - .resume = cortex_a8_resume, - .step = cortex_a8_step, - - .assert_reset = cortex_a8_assert_reset, - .deassert_reset = cortex_a8_deassert_reset, - .soft_reset_halt = NULL, - - .get_gdb_reg_list = armv4_5_get_gdb_reg_list, - - .read_memory = cortex_a8_read_memory, - .write_memory = cortex_a8_write_memory, - .bulk_write_memory = cortex_a8_bulk_write_memory, - .checksum_memory = arm7_9_checksum_memory, - .blank_check_memory = arm7_9_blank_check_memory, - - .run_algorithm = armv4_5_run_algorithm, - - .add_breakpoint = cortex_a8_add_breakpoint, - .remove_breakpoint = cortex_a8_remove_breakpoint, - .add_watchpoint = NULL, - .remove_watchpoint = NULL, - - .register_commands = cortex_a8_register_commands, - .target_create = cortex_a8_target_create, - .init_target = cortex_a8_init_target, - .examine = cortex_a8_examine, - .mrc = cortex_a8_mrc, - .mcr = cortex_a8_mcr, -}; - /* * FIXME do topology discovery using the ROM; don't * assume this is an OMAP3. @@ -126,12 +61,10 @@ target_type_t cortexa8_target = /* * Cortex-A8 Basic debug access, very low level assumes state is saved */ -int cortex_a8_init_debug_access(target_t *target) +static int cortex_a8_init_debug_access(struct target *target) { - /* get pointers to arch-specific information */ - armv4_5_common_t *armv4_5 = target->arch_info; - armv7a_common_t *armv7a = armv4_5->arch_info; - swjdp_common_t *swjdp = &armv7a->swjdp_info; + struct armv7a_common *armv7a = target_to_armv7a(target); + struct swjdp_common *swjdp = &armv7a->swjdp_info; int retval; uint32_t dummy; @@ -156,14 +89,17 @@ int cortex_a8_init_debug_access(target_t *target) return retval; } -int cortex_a8_exec_opcode(target_t *target, uint32_t opcode) +/* FIXME we waste a *LOT* of round-trips with needless DSCR reads, which + * slows down operations considerably. One good way to start reducing + * them would pass current values into and out of this routine. That + * should also help synch DCC read/write. + */ +static int cortex_a8_exec_opcode(struct target *target, uint32_t opcode) { uint32_t dscr; int retval; - /* get pointers to arch-specific information */ - armv4_5_common_t *armv4_5 = target->arch_info; - armv7a_common_t *armv7a = armv4_5->arch_info; - swjdp_common_t *swjdp = &armv7a->swjdp_info; + struct armv7a_common *armv7a = target_to_armv7a(target); + struct swjdp_common *swjdp = &armv7a->swjdp_info; LOG_DEBUG("exec opcode 0x%08" PRIx32, opcode); do @@ -199,14 +135,12 @@ int cortex_a8_exec_opcode(target_t *target, uint32_t opcode) Read core register with very few exec_opcode, fast but needs work_area. This can cause problems with MMU active. **************************************************************************/ -int cortex_a8_read_regs_through_mem(target_t *target, uint32_t address, +static int cortex_a8_read_regs_through_mem(struct target *target, uint32_t address, uint32_t * regfile) { int retval = ERROR_OK; - /* get pointers to arch-specific information */ - armv4_5_common_t *armv4_5 = target->arch_info; - armv7a_common_t *armv7a = armv4_5->arch_info; - swjdp_common_t *swjdp = &armv7a->swjdp_info; + struct armv7a_common *armv7a = target_to_armv7a(target); + struct swjdp_common *swjdp = &armv7a->swjdp_info; cortex_a8_dap_read_coreregister_u32(target, regfile, 0); cortex_a8_dap_write_coreregister_u32(target, address, 0); @@ -218,14 +152,12 @@ int cortex_a8_read_regs_through_mem(target_t *target, uint32_t address, return retval; } -int cortex_a8_read_cp(target_t *target, uint32_t *value, uint8_t CP, +static int cortex_a8_read_cp(struct target *target, uint32_t *value, uint8_t CP, uint8_t op1, uint8_t CRn, uint8_t CRm, uint8_t op2) { int retval; - /* get pointers to arch-specific information */ - armv4_5_common_t *armv4_5 = target->arch_info; - armv7a_common_t *armv7a = armv4_5->arch_info; - swjdp_common_t *swjdp = &armv7a->swjdp_info; + struct armv7a_common *armv7a = target_to_armv7a(target); + struct swjdp_common *swjdp = &armv7a->swjdp_info; cortex_a8_exec_opcode(target, ARMV4_5_MRC(CP, op1, 0, CRn, CRm, op2)); /* Move R0 to DTRTX */ @@ -238,16 +170,13 @@ int cortex_a8_read_cp(target_t *target, uint32_t *value, uint8_t CP, return retval; } -int cortex_a8_write_cp(target_t *target, uint32_t value, +static int cortex_a8_write_cp(struct target *target, uint32_t value, uint8_t CP, uint8_t op1, uint8_t CRn, uint8_t CRm, uint8_t op2) { int retval; uint32_t dscr; - - /* get pointers to arch-specific information */ - armv4_5_common_t *armv4_5 = target->arch_info; - armv7a_common_t *armv7a = armv4_5->arch_info; - swjdp_common_t *swjdp = &armv7a->swjdp_info; + struct armv7a_common *armv7a = target_to_armv7a(target); + struct swjdp_common *swjdp = &armv7a->swjdp_info; LOG_DEBUG("CP%i, CRn %i, value 0x%08" PRIx32, CP, CRn, value); @@ -270,19 +199,19 @@ int cortex_a8_write_cp(target_t *target, uint32_t value, return retval; } -int cortex_a8_read_cp15(target_t *target, uint32_t op1, uint32_t op2, +static int cortex_a8_read_cp15(struct target *target, uint32_t op1, uint32_t op2, uint32_t CRn, uint32_t CRm, uint32_t *value) { return cortex_a8_read_cp(target, value, 15, op1, CRn, CRm, op2); } -int cortex_a8_write_cp15(target_t *target, uint32_t op1, uint32_t op2, +static int cortex_a8_write_cp15(struct target *target, uint32_t op1, uint32_t op2, uint32_t CRn, uint32_t CRm, uint32_t value) { return cortex_a8_write_cp(target, value, 15, op1, CRn, CRm, op2); } -static int cortex_a8_mrc(target_t *target, int cpnum, uint32_t op1, uint32_t op2, uint32_t CRn, uint32_t CRm, uint32_t *value) +static int cortex_a8_mrc(struct target *target, int cpnum, uint32_t op1, uint32_t op2, uint32_t CRn, uint32_t CRm, uint32_t *value) { if (cpnum!=15) { @@ -292,7 +221,7 @@ static int cortex_a8_mrc(target_t *target, int cpnum, uint32_t op1, uint32_t op2 return cortex_a8_read_cp15(target, op1, op2, CRn, CRm, value); } -static int cortex_a8_mcr(target_t *target, int cpnum, uint32_t op1, uint32_t op2, uint32_t CRn, uint32_t CRm, uint32_t value) +static int cortex_a8_mcr(struct target *target, int cpnum, uint32_t op1, uint32_t op2, uint32_t CRn, uint32_t CRm, uint32_t value) { if (cpnum!=15) { @@ -304,34 +233,35 @@ static int cortex_a8_mcr(target_t *target, int cpnum, uint32_t op1, uint32_t op2 -int cortex_a8_dap_read_coreregister_u32(target_t *target, +static int cortex_a8_dap_read_coreregister_u32(struct target *target, uint32_t *value, int regnum) { int retval = ERROR_OK; uint8_t reg = regnum&0xFF; uint32_t dscr; + struct armv7a_common *armv7a = target_to_armv7a(target); + struct swjdp_common *swjdp = &armv7a->swjdp_info; - /* get pointers to arch-specific information */ - armv4_5_common_t *armv4_5 = target->arch_info; - armv7a_common_t *armv7a = armv4_5->arch_info; - swjdp_common_t *swjdp = &armv7a->swjdp_info; - - if (reg > 16) + if (reg > 17) return retval; if (reg < 15) { - /* Rn to DCCTX, MCR p14, 0, Rd, c0, c5, 0, 0xEE000E15 */ + /* Rn to DCCTX, "MCR p14, 0, Rn, c0, c5, 0" 0xEE00nE15 */ cortex_a8_exec_opcode(target, ARMV4_5_MCR(14, 0, reg, 0, 5, 0)); } else if (reg == 15) { + /* "MOV r0, r15"; then move r0 to DCCTX */ cortex_a8_exec_opcode(target, 0xE1A0000F); cortex_a8_exec_opcode(target, ARMV4_5_MCR(14, 0, 0, 0, 5, 0)); } - else if (reg == 16) + else { - cortex_a8_exec_opcode(target, ARMV4_5_MRS(0, 0)); + /* "MRS r0, CPSR" or "MRS r0, SPSR" + * then move r0 to DCCTX + */ + cortex_a8_exec_opcode(target, ARMV4_5_MRS(0, reg & 1)); cortex_a8_exec_opcode(target, ARMV4_5_MCR(14, 0, 0, 0, 5, 0)); } @@ -345,20 +275,19 @@ int cortex_a8_dap_read_coreregister_u32(target_t *target, retval = mem_ap_read_atomic_u32(swjdp, armv7a->debug_base + CPUDBG_DTRTX, value); + LOG_DEBUG("read DCC 0x%08" PRIx32, *value); return retval; } -int cortex_a8_dap_write_coreregister_u32(target_t *target, uint32_t value, int regnum) +static int cortex_a8_dap_write_coreregister_u32(struct target *target, + uint32_t value, int regnum) { int retval = ERROR_OK; uint8_t Rd = regnum&0xFF; uint32_t dscr; - - /* get pointers to arch-specific information */ - armv4_5_common_t *armv4_5 = target->arch_info; - armv7a_common_t *armv7a = armv4_5->arch_info; - swjdp_common_t *swjdp = &armv7a->swjdp_info; + struct armv7a_common *armv7a = target_to_armv7a(target); + struct swjdp_common *swjdp = &armv7a->swjdp_info; LOG_DEBUG("register %i, value 0x%08" PRIx32, regnum, value); @@ -372,43 +301,50 @@ int cortex_a8_dap_write_coreregister_u32(target_t *target, uint32_t value, int r cortex_a8_exec_opcode(target, ARMV4_5_MRC(14, 0, 0, 0, 5, 0)); } - if (Rd > 16) + if (Rd > 17) return retval; /* Write to DCCRX */ + LOG_DEBUG("write DCC 0x%08" PRIx32, value); retval = mem_ap_write_u32(swjdp, armv7a->debug_base + CPUDBG_DTRRX, value); if (Rd < 15) { - /* DCCRX to Rd, MCR p14, 0, Rd, c0, c5, 0, 0xEE000E15 */ + /* DCCRX to Rn, "MCR p14, 0, Rn, c0, c5, 0", 0xEE00nE15 */ cortex_a8_exec_opcode(target, ARMV4_5_MRC(14, 0, Rd, 0, 5, 0)); } else if (Rd == 15) { + /* DCCRX to R0, "MCR p14, 0, R0, c0, c5, 0", 0xEE000E15 + * then "mov r15, r0" + */ cortex_a8_exec_opcode(target, ARMV4_5_MRC(14, 0, 0, 0, 5, 0)); cortex_a8_exec_opcode(target, 0xE1A0F000); } - else if (Rd == 16) + else { + /* DCCRX to R0, "MCR p14, 0, R0, c0, c5, 0", 0xEE000E15 + * then "MSR CPSR_cxsf, r0" or "MSR SPSR_cxsf, r0" (all fields) + */ cortex_a8_exec_opcode(target, ARMV4_5_MRC(14, 0, 0, 0, 5, 0)); - cortex_a8_exec_opcode(target, ARMV4_5_MSR_GP(0, 0xF, 0)); - /* Execute a PrefetchFlush instruction through the ITR. */ - cortex_a8_exec_opcode(target, ARMV4_5_MCR(15, 0, 0, 7, 5, 4)); + cortex_a8_exec_opcode(target, ARMV4_5_MSR_GP(0, 0xF, Rd & 1)); + + /* "Prefetch flush" after modifying execution status in CPSR */ + if (Rd == 16) + cortex_a8_exec_opcode(target, + ARMV4_5_MCR(15, 0, 0, 7, 5, 4)); } return retval; } /* Write to memory mapped registers directly with no cache or mmu handling */ -int cortex_a8_dap_write_memap_register_u32(target_t *target, uint32_t address, uint32_t value) +static int cortex_a8_dap_write_memap_register_u32(struct target *target, uint32_t address, uint32_t value) { int retval; - - /* get pointers to arch-specific information */ - armv4_5_common_t *armv4_5 = target->arch_info; - armv7a_common_t *armv7a = armv4_5->arch_info; - swjdp_common_t *swjdp = &armv7a->swjdp_info; + struct armv7a_common *armv7a = target_to_armv7a(target); + struct swjdp_common *swjdp = &armv7a->swjdp_info; retval = mem_ap_write_atomic_u32(swjdp, address, value); @@ -416,23 +352,186 @@ int cortex_a8_dap_write_memap_register_u32(target_t *target, uint32_t address, u } /* - * Cortex-A8 Run control + * Cortex-A8 implementation of Debug Programmer's Model + * + * NOTE that in several of these cases the "stall" mode might be useful. + * It'd let us queue a few operations together... prepare/finish might + * be the places to enable/disable that mode. */ -int cortex_a8_poll(target_t *target) +static inline struct cortex_a8_common *dpm_to_a8(struct arm_dpm *dpm) { - int retval = ERROR_OK; + return container_of(dpm, struct cortex_a8_common, armv7a_common.dpm); +} + +static int cortex_a8_write_dcc(struct cortex_a8_common *a8, uint32_t data) +{ + LOG_DEBUG("write DCC 0x%08" PRIx32, data); + return mem_ap_write_u32(&a8->armv7a_common.swjdp_info, + a8->armv7a_common.debug_base + CPUDBG_DTRRX, data); +} + +static int cortex_a8_read_dcc(struct cortex_a8_common *a8, uint32_t *data) +{ + struct swjdp_common *swjdp = &a8->armv7a_common.swjdp_info; uint32_t dscr; - /* get pointers to arch-specific information */ - armv4_5_common_t *armv4_5 = target->arch_info; - armv7a_common_t *armv7a = armv4_5->arch_info; - cortex_a8_common_t *cortex_a8 = armv7a->arch_info; - swjdp_common_t *swjdp = &armv7a->swjdp_info; + int retval; + + /* Wait for DTRRXfull */ + do { + retval = mem_ap_read_atomic_u32(swjdp, + a8->armv7a_common.debug_base + CPUDBG_DSCR, + &dscr); + } while ((dscr & (1 << DSCR_DTR_TX_FULL)) == 0); + retval = mem_ap_read_atomic_u32(swjdp, + a8->armv7a_common.debug_base + CPUDBG_DTRTX, data); + LOG_DEBUG("read DCC 0x%08" PRIx32, *data); - enum target_state prev_target_state = target->state; + return retval; +} + +static int cortex_a8_dpm_prepare(struct arm_dpm *dpm) +{ + struct cortex_a8_common *a8 = dpm_to_a8(dpm); + struct swjdp_common *swjdp = &a8->armv7a_common.swjdp_info; + uint32_t dscr; + int retval; + + retval = mem_ap_read_atomic_u32(swjdp, + a8->armv7a_common.debug_base + CPUDBG_DSCR, + &dscr); + + /* this "should never happen" ... */ + if (dscr & (1 << DSCR_DTR_RX_FULL)) { + LOG_ERROR("DSCR_DTR_RX_FULL, dscr 0x%08" PRIx32, dscr); + /* Clear DCCRX */ + retval = cortex_a8_exec_opcode( + a8->armv7a_common.armv4_5_common.target, + ARMV4_5_MRC(14, 0, 0, 0, 5, 0)); + } + + return retval; +} + +static int cortex_a8_dpm_finish(struct arm_dpm *dpm) +{ + /* REVISIT what could be done here? */ + return ERROR_OK; +} + +static int cortex_a8_instr_write_data_dcc(struct arm_dpm *dpm, + uint32_t opcode, uint32_t data) +{ + struct cortex_a8_common *a8 = dpm_to_a8(dpm); + int retval; + retval = cortex_a8_write_dcc(a8, data); + + return cortex_a8_exec_opcode( + a8->armv7a_common.armv4_5_common.target, + opcode); +} + +static int cortex_a8_instr_write_data_r0(struct arm_dpm *dpm, + uint32_t opcode, uint32_t data) +{ + struct cortex_a8_common *a8 = dpm_to_a8(dpm); + int retval; + + retval = cortex_a8_write_dcc(a8, data); + + /* DCCRX to R0, "MCR p14, 0, R0, c0, c5, 0", 0xEE000E15 */ + retval = cortex_a8_exec_opcode( + a8->armv7a_common.armv4_5_common.target, + ARMV4_5_MRC(14, 0, 0, 0, 5, 0)); + + /* then the opcode, taking data from R0 */ + retval = cortex_a8_exec_opcode( + a8->armv7a_common.armv4_5_common.target, + opcode); + + return retval; +} + +static int cortex_a8_instr_cpsr_sync(struct arm_dpm *dpm) +{ + struct target *target = dpm->arm->target; + + /* "Prefetch flush" after modifying execution status in CPSR */ + return cortex_a8_exec_opcode(target, ARMV4_5_MCR(15, 0, 0, 7, 5, 4)); +} + +static int cortex_a8_instr_read_data_dcc(struct arm_dpm *dpm, + uint32_t opcode, uint32_t *data) +{ + struct cortex_a8_common *a8 = dpm_to_a8(dpm); + int retval; + + /* the opcode, writing data to DCC */ + retval = cortex_a8_exec_opcode( + a8->armv7a_common.armv4_5_common.target, + opcode); + + return cortex_a8_read_dcc(a8, data); +} + + +static int cortex_a8_instr_read_data_r0(struct arm_dpm *dpm, + uint32_t opcode, uint32_t *data) +{ + struct cortex_a8_common *a8 = dpm_to_a8(dpm); + int retval; + + /* the opcode, writing data to R0 */ + retval = cortex_a8_exec_opcode( + a8->armv7a_common.armv4_5_common.target, + opcode); + + /* write R0 to DCC */ + retval = cortex_a8_exec_opcode( + a8->armv7a_common.armv4_5_common.target, + ARMV4_5_MCR(14, 0, 0, 0, 5, 0)); + + return cortex_a8_read_dcc(a8, data); +} + +// static +int cortex_a8_dpm_setup(struct cortex_a8_common *a8, uint32_t didr) +{ + struct arm_dpm *dpm = &a8->armv7a_common.dpm; + + dpm->arm = &a8->armv7a_common.armv4_5_common; + dpm->didr = didr; + + dpm->prepare = cortex_a8_dpm_prepare; + dpm->finish = cortex_a8_dpm_finish; + + dpm->instr_write_data_dcc = cortex_a8_instr_write_data_dcc; + dpm->instr_write_data_r0 = cortex_a8_instr_write_data_r0; + dpm->instr_cpsr_sync = cortex_a8_instr_cpsr_sync; + + dpm->instr_read_data_dcc = cortex_a8_instr_read_data_dcc; + dpm->instr_read_data_r0 = cortex_a8_instr_read_data_r0; + + return arm_dpm_setup(dpm); +} + + +/* + * Cortex-A8 Run control + */ + +static int cortex_a8_poll(struct target *target) +{ + int retval = ERROR_OK; + uint32_t dscr; + struct cortex_a8_common *cortex_a8 = target_to_cortex_a8(target); + struct armv7a_common *armv7a = &cortex_a8->armv7a_common; + struct swjdp_common *swjdp = &armv7a->swjdp_info; + enum target_state prev_target_state = target->state; uint8_t saved_apsel = dap_ap_get_select(swjdp); + dap_ap_select(swjdp, swjdp_debugap); retval = mem_ap_read_atomic_u32(swjdp, armv7a->debug_base + CPUDBG_DSCR, &dscr); @@ -488,16 +587,12 @@ int cortex_a8_poll(target_t *target) return retval; } -int cortex_a8_halt(target_t *target) +static int cortex_a8_halt(struct target *target) { int retval = ERROR_OK; uint32_t dscr; - - /* get pointers to arch-specific information */ - armv4_5_common_t *armv4_5 = target->arch_info; - armv7a_common_t *armv7a = armv4_5->arch_info; - swjdp_common_t *swjdp = &armv7a->swjdp_info; - + struct armv7a_common *armv7a = target_to_armv7a(target); + struct swjdp_common *swjdp = &armv7a->swjdp_info; uint8_t saved_apsel = dap_ap_get_select(swjdp); dap_ap_select(swjdp, swjdp_debugap); @@ -530,15 +625,14 @@ out: return retval; } -int cortex_a8_resume(struct target_s *target, int current, +static int cortex_a8_resume(struct target *target, int current, uint32_t address, int handle_breakpoints, int debug_execution) { - /* get pointers to arch-specific information */ - armv4_5_common_t *armv4_5 = target->arch_info; - armv7a_common_t *armv7a = armv4_5->arch_info; - swjdp_common_t *swjdp = &armv7a->swjdp_info; + struct armv7a_common *armv7a = target_to_armv7a(target); + struct arm *armv4_5 = &armv7a->armv4_5_common; + struct swjdp_common *swjdp = &armv7a->swjdp_info; -// breakpoint_t *breakpoint = NULL; +// struct breakpoint *breakpoint = NULL; uint32_t resume_pc, dscr; uint8_t saved_apsel = dap_ap_get_select(swjdp); @@ -574,8 +668,7 @@ int cortex_a8_resume(struct target_s *target, int current, /* current = 1: continue on current pc, otherwise continue at
*/ resume_pc = buf_get_u32( - ARMV7A_CORE_REG_MODE(armv4_5->core_cache, - armv4_5->core_mode, 15).value, + armv4_5->core_cache->reg_list[15].value, 0, 32); if (!current) resume_pc = address; @@ -583,28 +676,30 @@ int cortex_a8_resume(struct target_s *target, int current, /* Make sure that the Armv7 gdb thumb fixups does not * kill the return address */ - if (armv7a->core_state == ARMV7A_STATE_ARM) + switch (armv4_5->core_state) { + case ARMV4_5_STATE_ARM: resume_pc &= 0xFFFFFFFC; - } - /* When the return address is loaded into PC - * bit 0 must be 1 to stay in Thumb state - */ - if (armv7a->core_state == ARMV7A_STATE_THUMB) - { + break; + case ARMV4_5_STATE_THUMB: + case ARM_STATE_THUMB_EE: + /* When the return address is loaded into PC + * bit 0 must be 1 to stay in Thumb state + */ resume_pc |= 0x1; + break; + case ARMV4_5_STATE_JAZELLE: + LOG_ERROR("How do I resume into Jazelle state??"); + return ERROR_FAIL; } LOG_DEBUG("resume pc = 0x%08" PRIx32, resume_pc); - buf_set_u32(ARMV7A_CORE_REG_MODE(armv4_5->core_cache, - armv4_5->core_mode, 15).value, + buf_set_u32(armv4_5->core_cache->reg_list[15].value, 0, 32, resume_pc); - ARMV7A_CORE_REG_MODE(armv4_5->core_cache, - armv4_5->core_mode, 15).dirty = 1; - ARMV7A_CORE_REG_MODE(armv4_5->core_cache, - armv4_5->core_mode, 15).valid = 1; + armv4_5->core_cache->reg_list[15].dirty = 1; + armv4_5->core_cache->reg_list[15].valid = 1; cortex_a8_restore_context(target); -// arm7_9_restore_context(target); TODO Context is currently NOT Properly restored + #if 0 /* the front-end may request us not to handle breakpoints */ if (handle_breakpoints) @@ -632,7 +727,7 @@ int cortex_a8_resume(struct target_s *target, int current, target->state = TARGET_RUNNING; /* registers are now invalid */ - armv4_5_invalidate_core_regs(target); + register_cache_invalidate(armv4_5->core_cache); if (!debug_execution) { @@ -652,24 +747,29 @@ int cortex_a8_resume(struct target_s *target, int current, return ERROR_OK; } -int cortex_a8_debug_entry(target_t *target) +static int cortex_a8_debug_entry(struct target *target) { int i; uint32_t regfile[16], pc, cpsr, dscr; int retval = ERROR_OK; - working_area_t *regfile_working_area = NULL; - - /* get pointers to arch-specific information */ - armv4_5_common_t *armv4_5 = target->arch_info; - armv7a_common_t *armv7a = armv4_5->arch_info; - cortex_a8_common_t *cortex_a8 = armv7a->arch_info; - swjdp_common_t *swjdp = &armv7a->swjdp_info; + struct working_area *regfile_working_area = NULL; + struct cortex_a8_common *cortex_a8 = target_to_cortex_a8(target); + struct armv7a_common *armv7a = target_to_armv7a(target); + struct arm *armv4_5 = &armv7a->armv4_5_common; + struct swjdp_common *swjdp = &armv7a->swjdp_info; + struct reg *reg; LOG_DEBUG("dscr = 0x%08" PRIx32, cortex_a8->cpudbg_dscr); /* Enable the ITR execution once we are in debug mode */ mem_ap_read_atomic_u32(swjdp, armv7a->debug_base + CPUDBG_DSCR, &dscr); + + /* REVISIT see A8 TRM 12.11.4 steps 2..3 -- make sure that any + * imprecise data aborts get discarded by issuing a Data + * Synchronization Barrier: ARMV4_5_MCR(15, 0, 0, 7, 10, 4). + */ + dscr |= (1 << DSCR_EXT_INT_EN); retval = mem_ap_write_atomic_u32(swjdp, armv7a->debug_base + CPUDBG_DSCR, dscr); @@ -677,22 +777,28 @@ int cortex_a8_debug_entry(target_t *target) /* Examine debug reason */ switch ((cortex_a8->cpudbg_dscr >> 2)&0xF) { - case 0: - case 4: + case 0: /* DRCR[0] write */ + case 4: /* EDBGRQ */ target->debug_reason = DBG_REASON_DBGRQ; break; - case 1: - case 3: + case 1: /* HW breakpoint */ + case 3: /* SW BKPT */ + case 5: /* vector catch */ target->debug_reason = DBG_REASON_BREAKPOINT; break; - case 10: + case 10: /* precise watchpoint */ target->debug_reason = DBG_REASON_WATCHPOINT; + /* REVISIT could collect WFAR later, to see just + * which instruction triggered the watchpoint. + */ break; default: target->debug_reason = DBG_REASON_UNDEFINED; break; } + /* REVISIT fast_reg_read is never set ... */ + /* Examine target state and mode */ if (cortex_a8->fast_reg_read) target_alloc_working_area(target, 64, ®file_working_area); @@ -700,6 +806,9 @@ int cortex_a8_debug_entry(target_t *target) /* First load register acessible through core debug port*/ if (!regfile_working_area) { + /* FIXME we don't actually need all these registers; + * reading them slows us down. Just R0, PC, CPSR... + */ for (i = 0; i <= 15; i++) cortex_a8_dap_read_coreregister_u32(target, ®file[i], i); @@ -713,32 +822,26 @@ int cortex_a8_debug_entry(target_t *target) target_free_working_area(target, regfile_working_area); } + /* read Current PSR */ cortex_a8_dap_read_coreregister_u32(target, &cpsr, 16); pc = regfile[15]; dap_ap_select(swjdp, swjdp_debugap); LOG_DEBUG("cpsr: %8.8" PRIx32, cpsr); - armv4_5->core_mode = cpsr & 0x1F; - armv7a->core_state = (cpsr & 0x20)?ARMV7A_STATE_THUMB:ARMV7A_STATE_ARM; + arm_set_cpsr(armv4_5, cpsr); + /* update cache */ for (i = 0; i <= ARM_PC; i++) { - buf_set_u32(ARMV7A_CORE_REG_MODE(armv4_5->core_cache, - armv4_5->core_mode, i).value, - 0, 32, regfile[i]); - ARMV7A_CORE_REG_MODE(armv4_5->core_cache, - armv4_5->core_mode, i).valid = 1; - ARMV7A_CORE_REG_MODE(armv4_5->core_cache, - armv4_5->core_mode, i).dirty = 0; - } - buf_set_u32(ARMV7A_CORE_REG_MODE(armv4_5->core_cache, - armv4_5->core_mode, 16).value, - 0, 32, cpsr); - ARMV7A_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 16).valid = 1; - ARMV7A_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 16).dirty = 0; + reg = arm_reg_current(armv4_5, i); + + buf_set_u32(reg->value, 0, 32, regfile[i]); + reg->valid = 1; + reg->dirty = 0; + } /* Fixup PC Resume Address */ - if (armv7a->core_state == ARMV7A_STATE_THUMB) + if (cpsr & (1 << 5)) { // T bit set for Thumb or ThumbEE state regfile[ARM_PC] -= 4; @@ -748,15 +851,12 @@ int cortex_a8_debug_entry(target_t *target) // ARM state regfile[ARM_PC] -= 8; } - buf_set_u32(ARMV7A_CORE_REG_MODE(armv4_5->core_cache, - armv4_5->core_mode, ARM_PC).value, - 0, 32, regfile[ARM_PC]); - ARMV7A_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 0) - .dirty = ARMV7A_CORE_REG_MODE(armv4_5->core_cache, - armv4_5->core_mode, 0).valid; - ARMV7A_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 15) - .dirty = ARMV7A_CORE_REG_MODE(armv4_5->core_cache, + reg = armv4_5->core_cache->reg_list + 15; + buf_set_u32(reg->value, 0, 32, regfile[ARM_PC]); + reg->dirty = reg->valid; + ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 15) + .dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 15).valid; #if 0 @@ -783,12 +883,10 @@ int cortex_a8_debug_entry(target_t *target) } -void cortex_a8_post_debug_entry(target_t *target) +static void cortex_a8_post_debug_entry(struct target *target) { - /* get pointers to arch-specific information */ - armv4_5_common_t *armv4_5 = target->arch_info; - armv7a_common_t *armv7a = armv4_5->arch_info; - cortex_a8_common_t *cortex_a8 = armv7a->arch_info; + struct cortex_a8_common *cortex_a8 = target_to_cortex_a8(target); + struct armv7a_common *armv7a = &cortex_a8->armv7a_common; // cortex_a8_read_cp(target, &cp15_control_register, 15, 0, 1, 0, 0); /* examine cp15 control reg */ @@ -817,14 +915,14 @@ void cortex_a8_post_debug_entry(target_t *target) } -int cortex_a8_step(struct target_s *target, int current, uint32_t address, +static int cortex_a8_step(struct target *target, int current, uint32_t address, int handle_breakpoints) { - /* get pointers to arch-specific information */ - armv4_5_common_t *armv4_5 = target->arch_info; - armv7a_common_t *armv7a = armv4_5->arch_info; - breakpoint_t *breakpoint = NULL; - breakpoint_t stepbreakpoint; + struct armv7a_common *armv7a = target_to_armv7a(target); + struct arm *armv4_5 = &armv7a->armv4_5_common; + struct breakpoint *breakpoint = NULL; + struct breakpoint stepbreakpoint; + struct reg *r; int timeout = 100; @@ -835,17 +933,14 @@ int cortex_a8_step(struct target_s *target, int current, uint32_t address, } /* current = 1: continue on current pc, otherwise continue at
*/ + r = armv4_5->core_cache->reg_list + 15; if (!current) { - buf_set_u32(ARMV7A_CORE_REG_MODE(armv4_5->core_cache, - armv4_5->core_mode, ARM_PC).value, - 0, 32, address); + buf_set_u32(r->value, 0, 32, address); } else { - address = buf_get_u32(ARMV7A_CORE_REG_MODE(armv4_5->core_cache, - armv4_5->core_mode, ARM_PC).value, - 0, 32); + address = buf_get_u32(r->value, 0, 32); } /* The front-end may request us not to handle breakpoints. @@ -854,17 +949,15 @@ int cortex_a8_step(struct target_s *target, int current, uint32_t address, */ handle_breakpoints = 1; if (handle_breakpoints) { - breakpoint = breakpoint_find(target, - buf_get_u32(ARMV7A_CORE_REG_MODE(armv4_5->core_cache, - armv4_5->core_mode, 15).value, - 0, 32)); + breakpoint = breakpoint_find(target, address); if (breakpoint) cortex_a8_unset_breakpoint(target, breakpoint); } /* Setup single step breakpoint */ stepbreakpoint.address = address; - stepbreakpoint.length = (armv7a->core_state == ARMV7A_STATE_THUMB) ? 2 : 4; + stepbreakpoint.length = (armv4_5->core_state == ARMV4_5_STATE_THUMB) + ? 2 : 4; stepbreakpoint.type = BKPT_HARD; stepbreakpoint.set = 0; @@ -897,33 +990,86 @@ int cortex_a8_step(struct target_s *target, int current, uint32_t address, return ERROR_OK; } -int cortex_a8_restore_context(target_t *target) +static int cortex_a8_restore_context(struct target *target) { - int i; uint32_t value; - - /* get pointers to arch-specific information */ - armv4_5_common_t *armv4_5 = target->arch_info; - armv7a_common_t *armv7a = armv4_5->arch_info; + struct armv7a_common *armv7a = target_to_armv7a(target); + struct reg_cache *cache = armv7a->armv4_5_common.core_cache; + unsigned max = cache->num_regs; + struct reg *r; + bool flushed, flush_cpsr = false; LOG_DEBUG(" "); if (armv7a->pre_restore_context) armv7a->pre_restore_context(target); - for (i = 15; i >= 0; i--) - { - if (ARMV7A_CORE_REG_MODE(armv4_5->core_cache, - armv4_5->core_mode, i).dirty) - { - value = buf_get_u32(ARMV7A_CORE_REG_MODE(armv4_5->core_cache, - armv4_5->core_mode, i).value, - 0, 32); + /* Flush all dirty registers from the cache, one mode at a time so + * that we write CPSR as little as possible. Save CPSR and R0 for + * last; they're used to change modes and write other registers. + * + * REVISIT be smarter: save eventual mode for last loop, don't + * need to write CPSR an extra time. + */ + do { + enum armv4_5_mode mode = ARMV4_5_MODE_ANY; + unsigned i; + + flushed = false; + + /* write dirty non-{R0,CPSR} registers sharing the same mode */ + for (i = max - 1, r = cache->reg_list + 1; i > 0; i--, r++) { + struct arm_reg *reg; + + if (!r->dirty || r == armv7a->armv4_5_common.cpsr) + continue; + reg = r->arch_info; + /* TODO Check return values */ - cortex_a8_dap_write_coreregister_u32(target, value, i); + + /* Pick a mode and update CPSR; else ignore this + * register if it's for a different mode than what + * we're handling on this pass. + * + * REVISIT don't distinguish SYS and USR modes. + * + * FIXME if we restore from FIQ mode, R8..R12 will + * get wrongly flushed onto FIQ shadows... + */ + if (mode == ARMV4_5_MODE_ANY) { + mode = reg->mode; + if (mode != ARMV4_5_MODE_ANY) { + cortex_a8_dap_write_coreregister_u32( + target, mode, 16); + flush_cpsr = true; + } + } else if (mode != reg->mode) + continue; + + /* Write this register */ + value = buf_get_u32(r->value, 0, 32); + cortex_a8_dap_write_coreregister_u32(target, value, + (reg->num == 16) ? 17 : reg->num); + r->dirty = false; + flushed = true; } + + } while (flushed); + + /* now flush CPSR if needed ... */ + r = armv7a->armv4_5_common.cpsr; + if (flush_cpsr || r->dirty) { + value = buf_get_u32(r->value, 0, 32); + cortex_a8_dap_write_coreregister_u32(target, value, 16); + r->dirty = false; } + /* ... and R0 always (it was dirtied when we saved context) */ + r = cache->reg_list + 0; + value = buf_get_u32(r->value, 0, 32); + cortex_a8_dap_write_coreregister_u32(target, value, 0); + r->dirty = false; + if (armv7a->post_restore_context) armv7a->post_restore_context(target); @@ -931,16 +1077,15 @@ int cortex_a8_restore_context(target_t *target) } +#if 0 /* * Cortex-A8 Core register functions */ - -int cortex_a8_load_core_reg_u32(struct target_s *target, int num, +static int cortex_a8_load_core_reg_u32(struct target *target, int num, armv4_5_mode_t mode, uint32_t * value) { int retval; - /* get pointers to arch-specific information */ - armv4_5_common_t *armv4_5 = target->arch_info; + struct arm *armv4_5 = target_to_armv4_5(target); if ((num <= ARM_CPSR)) { @@ -961,26 +1106,24 @@ int cortex_a8_load_core_reg_u32(struct target_s *target, int num, /* Register other than r0 - r14 uses r0 for access */ if (num > 14) - ARMV7A_CORE_REG_MODE(armv4_5->core_cache, + ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 0).dirty = - ARMV7A_CORE_REG_MODE(armv4_5->core_cache, + ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 0).valid; - ARMV7A_CORE_REG_MODE(armv4_5->core_cache, + ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 15).dirty = - ARMV7A_CORE_REG_MODE(armv4_5->core_cache, + ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 15).valid; return ERROR_OK; } -int cortex_a8_store_core_reg_u32(struct target_s *target, int num, +static int cortex_a8_store_core_reg_u32(struct target *target, int num, armv4_5_mode_t mode, uint32_t value) { int retval; // uint32_t reg; - - /* get pointers to arch-specific information */ - armv4_5_common_t *armv4_5 = target->arch_info; + struct arm *armv4_5 = target_to_armv4_5(target); #ifdef ARMV7_GDB_HACKS /* If the LR register is being modified, make sure it will put us @@ -999,9 +1142,9 @@ int cortex_a8_store_core_reg_u32(struct target_s *target, int num, if (retval != ERROR_OK) { LOG_ERROR("JTAG failure %i", retval); - ARMV7A_CORE_REG_MODE(armv4_5->core_cache, + ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, num).dirty = - ARMV7A_CORE_REG_MODE(armv4_5->core_cache, + ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, num).valid; return ERROR_JTAG_DEVICE_ERROR; } @@ -1014,45 +1157,121 @@ int cortex_a8_store_core_reg_u32(struct target_s *target, int num, return ERROR_OK; } +#endif + +static int cortex_a8_write_core_reg(struct target *target, struct reg *r, + int num, enum armv4_5_mode mode, uint32_t value); -int cortex_a8_read_core_reg(struct target_s *target, int num, - enum armv4_5_mode mode) +static int cortex_a8_read_core_reg(struct target *target, struct reg *r, + int num, enum armv4_5_mode mode) { uint32_t value; int retval; - armv4_5_common_t *armv4_5 = target->arch_info; - cortex_a8_dap_read_coreregister_u32(target, &value, num); + struct arm *armv4_5 = target_to_armv4_5(target); + struct reg *cpsr_r = NULL; + uint32_t cpsr = 0; + unsigned cookie = num; - if ((retval = jtag_execute_queue()) != ERROR_OK) - { - return retval; + /* avoid some needless mode changes + * FIXME move some of these to shared ARM code... + */ + if (mode != armv4_5->core_mode) { + if ((armv4_5->core_mode == ARMV4_5_MODE_SYS) + && (mode == ARMV4_5_MODE_USR)) + mode = ARMV4_5_MODE_ANY; + else if ((mode != ARMV4_5_MODE_FIQ) && (num <= 12)) + mode = ARMV4_5_MODE_ANY; + + if (mode != ARMV4_5_MODE_ANY) { + cpsr_r = armv4_5->cpsr; + cpsr = buf_get_u32(cpsr_r->value, 0, 32); + cortex_a8_write_core_reg(target, cpsr_r, + 16, ARMV4_5_MODE_ANY, mode); + } } - ARMV7A_CORE_REG_MODE(armv4_5->core_cache, mode, num).valid = 1; - ARMV7A_CORE_REG_MODE(armv4_5->core_cache, mode, num).dirty = 0; - buf_set_u32(ARMV7A_CORE_REG_MODE(armv4_5->core_cache, - mode, num).value, 0, 32, value); + if (num == 16) { + switch (mode) { + case ARMV4_5_MODE_USR: + case ARMV4_5_MODE_SYS: + case ARMV4_5_MODE_ANY: + /* CPSR */ + break; + default: + /* SPSR */ + cookie++; + break; + } + } - return ERROR_OK; + cortex_a8_dap_read_coreregister_u32(target, &value, cookie); + retval = jtag_execute_queue(); + if (retval == ERROR_OK) { + r->valid = 1; + r->dirty = 0; + buf_set_u32(r->value, 0, 32, value); + } + + if (cpsr_r) + cortex_a8_write_core_reg(target, cpsr_r, + 16, ARMV4_5_MODE_ANY, cpsr); + return retval; } -int cortex_a8_write_core_reg(struct target_s *target, int num, - enum armv4_5_mode mode, uint32_t value) +static int cortex_a8_write_core_reg(struct target *target, struct reg *r, + int num, enum armv4_5_mode mode, uint32_t value) { int retval; - armv4_5_common_t *armv4_5 = target->arch_info; + struct arm *armv4_5 = target_to_armv4_5(target); + struct reg *cpsr_r = NULL; + uint32_t cpsr = 0; + unsigned cookie = num; - cortex_a8_dap_write_coreregister_u32(target, value, num); - if ((retval = jtag_execute_queue()) != ERROR_OK) - { - return retval; + /* avoid some needless mode changes + * FIXME move some of these to shared ARM code... + */ + if (mode != armv4_5->core_mode) { + if ((armv4_5->core_mode == ARMV4_5_MODE_SYS) + && (mode == ARMV4_5_MODE_USR)) + mode = ARMV4_5_MODE_ANY; + else if ((mode != ARMV4_5_MODE_FIQ) && (num <= 12)) + mode = ARMV4_5_MODE_ANY; + + if (mode != ARMV4_5_MODE_ANY) { + cpsr_r = armv4_5->cpsr; + cpsr = buf_get_u32(cpsr_r->value, 0, 32); + cortex_a8_write_core_reg(target, cpsr_r, + 16, ARMV4_5_MODE_ANY, mode); + } } - ARMV7A_CORE_REG_MODE(armv4_5->core_cache, mode, num).valid = 1; - ARMV7A_CORE_REG_MODE(armv4_5->core_cache, mode, num).dirty = 0; - return ERROR_OK; + if (num == 16) { + switch (mode) { + case ARMV4_5_MODE_USR: + case ARMV4_5_MODE_SYS: + case ARMV4_5_MODE_ANY: + /* CPSR */ + break; + default: + /* SPSR */ + cookie++; + break; + } + } + + cortex_a8_dap_write_coreregister_u32(target, value, cookie); + if ((retval = jtag_execute_queue()) == ERROR_OK) { + buf_set_u32(r->value, 0, 32, value); + r->valid = 1; + r->dirty = 0; + } + + if (cpsr_r) + cortex_a8_write_core_reg(target, cpsr_r, + 16, ARMV4_5_MODE_ANY, cpsr); + return retval; } @@ -1061,20 +1280,16 @@ int cortex_a8_write_core_reg(struct target_s *target, int num, */ /* Setup hardware Breakpoint Register Pair */ -int cortex_a8_set_breakpoint(struct target_s *target, - breakpoint_t *breakpoint, uint8_t matchmode) +static int cortex_a8_set_breakpoint(struct target *target, + struct breakpoint *breakpoint, uint8_t matchmode) { int retval; int brp_i=0; uint32_t control; uint8_t byte_addr_select = 0x0F; - - - /* get pointers to arch-specific information */ - armv4_5_common_t *armv4_5 = target->arch_info; - armv7a_common_t *armv7a = armv4_5->arch_info; - cortex_a8_common_t *cortex_a8 = armv7a->arch_info; - cortex_a8_brp_t * brp_list = cortex_a8->brp_list; + struct cortex_a8_common *cortex_a8 = target_to_cortex_a8(target); + struct armv7a_common *armv7a = &cortex_a8->armv7a_common; + struct cortex_a8_brp * brp_list = cortex_a8->brp_list; if (breakpoint->set) { @@ -1089,7 +1304,7 @@ int cortex_a8_set_breakpoint(struct target_s *target, if (brp_i >= cortex_a8->brp_num) { LOG_ERROR("ERROR Can not find free Breakpoint Register Pair"); - exit(-1); + return ERROR_FAIL; } breakpoint->set = brp_i + 1; if (breakpoint->length == 2) @@ -1140,14 +1355,12 @@ int cortex_a8_set_breakpoint(struct target_s *target, return ERROR_OK; } -int cortex_a8_unset_breakpoint(struct target_s *target, breakpoint_t *breakpoint) +static int cortex_a8_unset_breakpoint(struct target *target, struct breakpoint *breakpoint) { int retval; - /* get pointers to arch-specific information */ - armv4_5_common_t *armv4_5 = target->arch_info; - armv7a_common_t *armv7a = armv4_5->arch_info; - cortex_a8_common_t *cortex_a8 = armv7a->arch_info; - cortex_a8_brp_t * brp_list = cortex_a8->brp_list; + struct cortex_a8_common *cortex_a8 = target_to_cortex_a8(target); + struct armv7a_common *armv7a = &cortex_a8->armv7a_common; + struct cortex_a8_brp * brp_list = cortex_a8->brp_list; if (!breakpoint->set) { @@ -1200,12 +1413,10 @@ int cortex_a8_unset_breakpoint(struct target_s *target, breakpoint_t *breakpoint return ERROR_OK; } -int cortex_a8_add_breakpoint(struct target_s *target, breakpoint_t *breakpoint) +static int cortex_a8_add_breakpoint(struct target *target, + struct breakpoint *breakpoint) { - /* get pointers to arch-specific information */ - armv4_5_common_t *armv4_5 = target->arch_info; - armv7a_common_t *armv7a = armv4_5->arch_info; - cortex_a8_common_t *cortex_a8 = armv7a->arch_info; + struct cortex_a8_common *cortex_a8 = target_to_cortex_a8(target); if ((breakpoint->type == BKPT_HARD) && (cortex_a8->brp_num_available < 1)) { @@ -1220,12 +1431,9 @@ int cortex_a8_add_breakpoint(struct target_s *target, breakpoint_t *breakpoint) return ERROR_OK; } -int cortex_a8_remove_breakpoint(struct target_s *target, breakpoint_t *breakpoint) +static int cortex_a8_remove_breakpoint(struct target *target, struct breakpoint *breakpoint) { - /* get pointers to arch-specific information */ - armv4_5_common_t *armv4_5 = target->arch_info; - armv7a_common_t *armv7a = armv4_5->arch_info; - cortex_a8_common_t *cortex_a8 = armv7a->arch_info; + struct cortex_a8_common *cortex_a8 = target_to_cortex_a8(target); #if 0 /* It is perfectly possible to remove brakpoints while the taget is running */ @@ -1253,20 +1461,21 @@ int cortex_a8_remove_breakpoint(struct target_s *target, breakpoint_t *breakpoin * Cortex-A8 Reset fuctions */ -int cortex_a8_assert_reset(target_t *target) +static int cortex_a8_assert_reset(struct target *target) { + struct armv7a_common *armv7a = target_to_armv7a(target); LOG_DEBUG(" "); /* registers are now invalid */ - armv4_5_invalidate_core_regs(target); + register_cache_invalidate(armv7a->armv4_5_common.core_cache); target->state = TARGET_RESET; return ERROR_OK; } -int cortex_a8_deassert_reset(target_t *target) +static int cortex_a8_deassert_reset(struct target *target) { LOG_DEBUG(" "); @@ -1288,26 +1497,19 @@ int cortex_a8_deassert_reset(target_t *target) * ap number for every access. */ -int cortex_a8_read_memory(struct target_s *target, uint32_t address, +static int cortex_a8_read_memory(struct target *target, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer) { - /* get pointers to arch-specific information */ - armv4_5_common_t *armv4_5 = target->arch_info; - armv7a_common_t *armv7a = armv4_5->arch_info; - swjdp_common_t *swjdp = &armv7a->swjdp_info; - - int retval = ERROR_OK; - - /* sanitize arguments */ - if (((size != 4) && (size != 2) && (size != 1)) || (count == 0) || !(buffer)) - return ERROR_INVALID_ARGUMENTS; + struct armv7a_common *armv7a = target_to_armv7a(target); + struct swjdp_common *swjdp = &armv7a->swjdp_info; + int retval = ERROR_INVALID_ARGUMENTS; /* cortex_a8 handles unaligned memory access */ // ??? dap_ap_select(swjdp, swjdp_memoryap); - switch (size) - { + if (count && buffer) { + switch (size) { case 4: retval = mem_ap_read_buf_u32(swjdp, buffer, 4 * count, address); break; @@ -1317,32 +1519,23 @@ int cortex_a8_read_memory(struct target_s *target, uint32_t address, case 1: retval = mem_ap_read_buf_u8(swjdp, buffer, count, address); break; - default: - LOG_ERROR("BUG: we shouldn't get here"); - exit(-1); + } } return retval; } -int cortex_a8_write_memory(struct target_s *target, uint32_t address, +static int cortex_a8_write_memory(struct target *target, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer) { - /* get pointers to arch-specific information */ - armv4_5_common_t *armv4_5 = target->arch_info; - armv7a_common_t *armv7a = armv4_5->arch_info; - swjdp_common_t *swjdp = &armv7a->swjdp_info; - - int retval; - - /* sanitize arguments */ - if (((size != 4) && (size != 2) && (size != 1)) || (count == 0) || !(buffer)) - return ERROR_INVALID_ARGUMENTS; + struct armv7a_common *armv7a = target_to_armv7a(target); + struct swjdp_common *swjdp = &armv7a->swjdp_info; + int retval = ERROR_INVALID_ARGUMENTS; // ??? dap_ap_select(swjdp, swjdp_memoryap); - switch (size) - { + if (count && buffer) { + switch (size) { case 4: retval = mem_ap_write_buf_u32(swjdp, buffer, 4 * count, address); break; @@ -1352,12 +1545,10 @@ int cortex_a8_write_memory(struct target_s *target, uint32_t address, case 1: retval = mem_ap_write_buf_u8(swjdp, buffer, count, address); break; - default: - LOG_ERROR("BUG: we shouldn't get here"); - exit(-1); + } } - if (target->state == TARGET_HALTED) + if (retval == ERROR_OK && target->state == TARGET_HALTED) { /* The Cache handling will NOT work with MMU active, the wrong addresses will be invalidated */ /* invalidate I-Cache */ @@ -1381,14 +1572,14 @@ int cortex_a8_write_memory(struct target_s *target, uint32_t address, return retval; } -int cortex_a8_bulk_write_memory(target_t *target, uint32_t address, +static int cortex_a8_bulk_write_memory(struct target *target, uint32_t address, uint32_t count, uint8_t *buffer) { return cortex_a8_write_memory(target, address, 4, count, buffer); } -int cortex_a8_dcc_read(swjdp_common_t *swjdp, uint8_t *value, uint8_t *ctrl) +static int cortex_a8_dcc_read(struct swjdp_common *swjdp, uint8_t *value, uint8_t *ctrl) { #if 0 u16 dcrdr; @@ -1411,16 +1602,14 @@ int cortex_a8_dcc_read(swjdp_common_t *swjdp, uint8_t *value, uint8_t *ctrl) } -int cortex_a8_handle_target_request(void *priv) +static int cortex_a8_handle_target_request(void *priv) { - target_t *target = priv; - if (!target->type->examined) - return ERROR_OK; - armv4_5_common_t *armv4_5 = target->arch_info; - armv7a_common_t *armv7a = armv4_5->arch_info; - swjdp_common_t *swjdp = &armv7a->swjdp_info; - + struct target *target = priv; + struct armv7a_common *armv7a = target_to_armv7a(target); + struct swjdp_common *swjdp = &armv7a->swjdp_info; + if (!target_was_examined(target)) + return ERROR_OK; if (!target->dbg_msg_enabled) return ERROR_OK; @@ -1455,15 +1644,11 @@ int cortex_a8_handle_target_request(void *priv) * Cortex-A8 target information and configuration */ -int cortex_a8_examine(struct target_s *target) +static int cortex_a8_examine_first(struct target *target) { - /* get pointers to arch-specific information */ - armv4_5_common_t *armv4_5 = target->arch_info; - armv7a_common_t *armv7a = armv4_5->arch_info; - cortex_a8_common_t *cortex_a8 = armv7a->arch_info; - swjdp_common_t *swjdp = &armv7a->swjdp_info; - - + struct cortex_a8_common *cortex_a8 = target_to_cortex_a8(target); + struct armv7a_common *armv7a = &cortex_a8->armv7a_common; + struct swjdp_common *swjdp = &armv7a->swjdp_info; int i; int retval = ERROR_OK; uint32_t didr, ctypr, ttypr, cpuid; @@ -1515,7 +1700,7 @@ int cortex_a8_examine(struct target_s *target) cortex_a8->brp_num = ((didr >> 24) & 0x0F) + 1; cortex_a8->brp_num_context = ((didr >> 20) & 0x0F) + 1; cortex_a8->brp_num_available = cortex_a8->brp_num; - cortex_a8->brp_list = calloc(cortex_a8->brp_num, sizeof(cortex_a8_brp_t)); + cortex_a8->brp_list = calloc(cortex_a8->brp_num, sizeof(struct cortex_a8_brp)); // cortex_a8->brb_enabled = ????; for (i = 0; i < cortex_a8->brp_num; i++) { @@ -1532,7 +1717,7 @@ int cortex_a8_examine(struct target_s *target) /* Setup Watchpoint Register Pairs */ cortex_a8->wrp_num = ((didr >> 28) & 0x0F) + 1; cortex_a8->wrp_num_available = cortex_a8->wrp_num; - cortex_a8->wrp_list = calloc(cortex_a8->wrp_num, sizeof(cortex_a8_wrp_t)); + cortex_a8->wrp_list = calloc(cortex_a8->wrp_num, sizeof(struct cortex_a8_wrp)); for (i = 0; i < cortex_a8->wrp_num; i++) { cortex_a8->wrp_list[i].used = 0; @@ -1544,10 +1729,21 @@ int cortex_a8_examine(struct target_s *target) LOG_DEBUG("Configured %i hw breakpoint pairs and %i hw watchpoint pairs", cortex_a8->brp_num , cortex_a8->wrp_num); - /* Configure core debug access */ - cortex_a8_init_debug_access(target); + target_set_examined(target); + return ERROR_OK; +} + +static int cortex_a8_examine(struct target *target) +{ + int retval = ERROR_OK; - target->type->examined = 1; + /* don't re-probe hardware after each reset */ + if (!target_was_examined(target)) + retval = cortex_a8_examine_first(target); + + /* Configure core debug access */ + if (retval == ERROR_OK) + retval = cortex_a8_init_debug_access(target); return retval; } @@ -1556,46 +1752,39 @@ int cortex_a8_examine(struct target_s *target) * Cortex-A8 target creation and initialization */ -void cortex_a8_build_reg_cache(target_t *target) +static void cortex_a8_build_reg_cache(struct target *target) { - reg_cache_t **cache_p = register_get_last_cache_p(&target->reg_cache); - /* get pointers to arch-specific information */ - armv4_5_common_t *armv4_5 = target->arch_info; + struct reg_cache **cache_p = register_get_last_cache_p(&target->reg_cache); + struct arm *armv4_5 = target_to_armv4_5(target); + + armv4_5->core_type = ARM_MODE_MON; (*cache_p) = armv4_5_build_reg_cache(target, armv4_5); - armv4_5->core_cache = (*cache_p); } -int cortex_a8_init_target(struct command_context_s *cmd_ctx, - struct target_s *target) +static int cortex_a8_init_target(struct command_context *cmd_ctx, + struct target *target) { cortex_a8_build_reg_cache(target); return ERROR_OK; } -int cortex_a8_init_arch_info(target_t *target, - cortex_a8_common_t *cortex_a8, jtag_tap_t *tap) +static int cortex_a8_init_arch_info(struct target *target, + struct cortex_a8_common *cortex_a8, struct jtag_tap *tap) { - armv4_5_common_t *armv4_5; - armv7a_common_t *armv7a; - - armv7a = &cortex_a8->armv7a_common; - armv4_5 = &armv7a->armv4_5_common; - swjdp_common_t *swjdp = &armv7a->swjdp_info; + struct armv7a_common *armv7a = &cortex_a8->armv7a_common; + struct arm *armv4_5 = &armv7a->armv4_5_common; + struct swjdp_common *swjdp = &armv7a->swjdp_info; - /* Setup cortex_a8_common_t */ + /* Setup struct cortex_a8_common */ cortex_a8->common_magic = CORTEX_A8_COMMON_MAGIC; - cortex_a8->arch_info = NULL; - armv7a->arch_info = cortex_a8; armv4_5->arch_info = armv7a; - armv4_5_init_arch_info(target, armv4_5); - /* prepare JTAG information for the new target */ cortex_a8->jtag_info.tap = tap; cortex_a8->jtag_info.scann_size = 4; -LOG_DEBUG(" "); + swjdp->dp_select_value = -1; swjdp->ap_csw_value = -1; swjdp->ap_tar_value = -1; @@ -1631,43 +1820,38 @@ LOG_DEBUG(" "); armv4_5->read_core_reg = cortex_a8_read_core_reg; armv4_5->write_core_reg = cortex_a8_write_core_reg; -// armv4_5->full_context = arm7_9_full_context; -// armv4_5->load_core_reg_u32 = cortex_a8_load_core_reg_u32; -// armv4_5->store_core_reg_u32 = cortex_a8_store_core_reg_u32; -// armv4_5->read_core_reg = armv4_5_read_core_reg; /* this is default */ -// armv4_5->write_core_reg = armv4_5_write_core_reg; + /* REVISIT v7a setup should be in a v7a-specific routine */ + armv4_5_init_arch_info(target, armv4_5); + armv7a->common_magic = ARMV7_COMMON_MAGIC; target_register_timer_callback(cortex_a8_handle_target_request, 1, 1, target); return ERROR_OK; } -int cortex_a8_target_create(struct target_s *target, Jim_Interp *interp) +static int cortex_a8_target_create(struct target *target, Jim_Interp *interp) { - cortex_a8_common_t *cortex_a8 = calloc(1, sizeof(cortex_a8_common_t)); + struct cortex_a8_common *cortex_a8 = calloc(1, sizeof(struct cortex_a8_common)); cortex_a8_init_arch_info(target, cortex_a8, target->tap); return ERROR_OK; } -static int cortex_a8_handle_cache_info_command(struct command_context_s *cmd_ctx, - char *cmd, char **args, int argc) +COMMAND_HANDLER(cortex_a8_handle_cache_info_command) { - target_t *target = get_current_target(cmd_ctx); - armv4_5_common_t *armv4_5 = target->arch_info; - armv7a_common_t *armv7a = armv4_5->arch_info; + struct target *target = get_current_target(CMD_CTX); + struct armv7a_common *armv7a = target_to_armv7a(target); - return armv4_5_handle_cache_info_command(cmd_ctx, + return armv4_5_handle_cache_info_command(CMD_CTX, &armv7a->armv4_5_mmu.armv4_5_cache); } -static int cortex_a8_handle_dbginit_command(struct command_context_s *cmd_ctx, - char *cmd, char **args, int argc) +COMMAND_HANDLER(cortex_a8_handle_dbginit_command) { - target_t *target = get_current_target(cmd_ctx); + struct target *target = get_current_target(CMD_CTX); cortex_a8_init_debug_access(target); @@ -1675,9 +1859,9 @@ static int cortex_a8_handle_dbginit_command(struct command_context_s *cmd_ctx, } -int cortex_a8_register_commands(struct command_context_s *cmd_ctx) +static int cortex_a8_register_commands(struct command_context *cmd_ctx) { - command_t *cortex_a8_cmd; + struct command *cortex_a8_cmd; int retval = ERROR_OK; armv4_5_register_commands(cmd_ctx); @@ -1697,3 +1881,43 @@ int cortex_a8_register_commands(struct command_context_s *cmd_ctx) return retval; } + +struct target_type cortexa8_target = { + .name = "cortex_a8", + + .poll = cortex_a8_poll, + .arch_state = armv7a_arch_state, + + .target_request_data = NULL, + + .halt = cortex_a8_halt, + .resume = cortex_a8_resume, + .step = cortex_a8_step, + + .assert_reset = cortex_a8_assert_reset, + .deassert_reset = cortex_a8_deassert_reset, + .soft_reset_halt = NULL, + + .get_gdb_reg_list = armv4_5_get_gdb_reg_list, + + .read_memory = cortex_a8_read_memory, + .write_memory = cortex_a8_write_memory, + .bulk_write_memory = cortex_a8_bulk_write_memory, + + .checksum_memory = arm_checksum_memory, + .blank_check_memory = arm_blank_check_memory, + + .run_algorithm = armv4_5_run_algorithm, + + .add_breakpoint = cortex_a8_add_breakpoint, + .remove_breakpoint = cortex_a8_remove_breakpoint, + .add_watchpoint = NULL, + .remove_watchpoint = NULL, + + .register_commands = cortex_a8_register_commands, + .target_create = cortex_a8_target_create, + .init_target = cortex_a8_init_target, + .examine = cortex_a8_examine, + .mrc = cortex_a8_mrc, + .mcr = cortex_a8_mcr, +};