X-Git-Url: https://review.openocd.org/gitweb?a=blobdiff_plain;f=src%2Ftarget%2Fcortex_a.h;h=1c63588e2b2913a240c5b67215c1877aa12bae37;hb=79d0f1345b8d68ff522f21451860c74c8f1018ca;hp=e124a9e07ccaadb6998177d4b1f05a91ab8bd823;hpb=987201c6dc4329c79057d6057a451e8e2c3568dc;p=openocd.git

diff --git a/src/target/cortex_a.h b/src/target/cortex_a.h
index e124a9e07c..1c63588e2b 100644
--- a/src/target/cortex_a.h
+++ b/src/target/cortex_a.h
@@ -60,6 +60,11 @@ enum cortex_a_isrmasking_mode {
 	CORTEX_A_ISRMASK_ON,
 };
 
+enum cortex_a_dacrfixup_mode {
+	CORTEX_A_DACRFIXUP_OFF,
+	CORTEX_A_DACRFIXUP_ON
+};
+
 struct cortex_a_brp {
 	int used;
 	int type;
@@ -70,7 +75,6 @@ struct cortex_a_brp {
 
 struct cortex_a_common {
 	int common_magic;
-	struct arm_jtag jtag_info;
 
 	/* Context information */
 	uint32_t cpudbg_dscr;
@@ -79,9 +83,12 @@ struct cortex_a_common {
 	uint32_t cp15_control_reg;
 	/* latest cp15 register value written and cpsr processor mode */
 	uint32_t cp15_control_reg_curr;
+	/* auxiliary control reg */
+	uint32_t cp15_aux_control_reg;
+	/* DACR */
+	uint32_t cp15_dacr_reg;
 	enum arm_mode curr_mode;
 
-
 	/* Breakpoint register pairs */
 	int brp_num_context;
 	int brp_num;
@@ -97,6 +104,7 @@ struct cortex_a_common {
 	uint32_t didr;
 
 	enum cortex_a_isrmasking_mode isrmasking_mode;
+	enum cortex_a_dacrfixup_mode dacrfixup_mode;
 
 	struct armv7a_common armv7a_common;