X-Git-Url: https://review.openocd.org/gitweb?a=blobdiff_plain;f=src%2Ftarget%2Farmv8_dpm.c;h=f4e7a07996c651546c92812b04f4f085a76305cd;hb=c26bbf7a1b2a11e9cc369536332bff2faa223da8;hp=acfd1bcdf8d510b8d73f9d3a3ff1284de80925e6;hpb=06ba5492df66e997eafe294fced505b11e67f2fc;p=openocd.git

diff --git a/src/target/armv8_dpm.c b/src/target/armv8_dpm.c
index acfd1bcdf8..f4e7a07996 100644
--- a/src/target/armv8_dpm.c
+++ b/src/target/armv8_dpm.c
@@ -51,17 +51,11 @@ enum arm_state armv8_dpm_get_core_state(struct arm_dpm *dpm)
 {
 	int el = (dpm->dscr >> 8) & 0x3;
 	int rw = (dpm->dscr >> 10) & 0xF;
-	int pos;
 
 	dpm->last_el = el;
 
-	/* find the first '0' in DSCR.RW */
-	for (pos = 3; pos >= 0; pos--) {
-		if ((rw & (1 << pos)) == 0)
-			break;
-	}
-
-	if (el > pos)
+	/* In Debug state, each bit gives the current Execution state of each EL */
+	if ((rw >> el) & 0b1)
 		return ARM_STATE_AARCH64;
 
 	return ARM_STATE_ARM;
@@ -71,7 +65,6 @@ enum arm_state armv8_dpm_get_core_state(struct arm_dpm *dpm)
 
 static int dpmv8_write_dcc(struct armv8_common *armv8, uint32_t data)
 {
-	LOG_DEBUG("write DCC 0x%08" PRIx32, data);
 	return mem_ap_write_u32(armv8->debug_ap,
 				armv8->debug_base + CPUV8_DBG_DTRRX, data);
 }
@@ -79,7 +72,6 @@ static int dpmv8_write_dcc(struct armv8_common *armv8, uint32_t data)
 static int dpmv8_write_dcc_64(struct armv8_common *armv8, uint64_t data)
 {
 	int ret;
-	LOG_DEBUG("write DCC 0x%016" PRIx64, data);
 	ret = mem_ap_write_u32(armv8->debug_ap,
 			       armv8->debug_base + CPUV8_DBG_DTRRX, data);
 	if (ret == ERROR_OK)
@@ -116,7 +108,6 @@ static int dpmv8_read_dcc(struct armv8_common *armv8, uint32_t *data,
 					    data);
 	if (retval != ERROR_OK)
 		return retval;
-	LOG_DEBUG("read DCC 0x%08" PRIx32, *data);
 
 	if (dscr_p)
 		*dscr_p = dscr;
@@ -161,7 +152,6 @@ static int dpmv8_read_dcc_64(struct armv8_common *armv8, uint64_t *data,
 		return retval;
 
 	*data = *(uint32_t *)data | (uint64_t)higher << 32;
-	LOG_DEBUG("read DCC 0x%16.16" PRIx64, *data);
 
 	if (dscr_p)
 		*dscr_p = dscr;
@@ -220,8 +210,6 @@ static int dpmv8_exec_opcode(struct arm_dpm *dpm,
 	uint32_t dscr = dpm->dscr;
 	int retval;
 
-	LOG_DEBUG("exec opcode 0x%08" PRIx32, opcode);
-
 	if (p_dscr)
 		dscr = *p_dscr;
 
@@ -730,14 +718,22 @@ int armv8_dpm_read_current_registers(struct arm_dpm *dpm)
 	cache = arm->core_cache;
 
 	/* read R0 first (it's used for scratch), then CPSR */
-	r = cache->reg_list + 0;
+	r = cache->reg_list + ARMV8_R0;
 	if (!r->valid) {
-		retval = dpmv8_read_reg(dpm, r, 0);
+		retval = dpmv8_read_reg(dpm, r, ARMV8_R0);
 		if (retval != ERROR_OK)
 			goto fail;
 	}
 	r->dirty = true;
 
+	/* read R1, too, it will be clobbered during memory access */
+	r = cache->reg_list + ARMV8_R1;
+	if (!r->valid) {
+		retval = dpmv8_read_reg(dpm, r, ARMV8_R1);
+		if (retval != ERROR_OK)
+			goto fail;
+	}
+
 	/* read cpsr to r0 and get it back */
 	retval = dpm->instr_read_data_r0(dpm,
 			armv8_opcode(armv8, READ_REG_DSPSR), &cpsr);
@@ -747,7 +743,7 @@ int armv8_dpm_read_current_registers(struct arm_dpm *dpm)
 	/* update core mode and state */
 	armv8_set_cpsr(arm, cpsr);
 
-	for (unsigned int i = 1; i < cache->num_regs ; i++) {
+	for (unsigned int i = ARMV8_PC; i < cache->num_regs ; i++) {
 		struct arm_reg *arm_reg;
 
 		r = armv8_reg_current(arm, i);
@@ -1316,6 +1312,8 @@ void armv8_dpm_handle_exception(struct arm_dpm *dpm)
 	core_state = armv8_dpm_get_core_state(dpm);
 	armv8_select_opcodes(armv8, core_state == ARM_STATE_AARCH64);
 	armv8_select_reg_access(armv8, core_state == ARM_STATE_AARCH64);
+
+	armv8_dpm_modeswitch(dpm, ARM_MODE_ANY);
 }
 
 /*----------------------------------------------------------------------*/