X-Git-Url: https://review.openocd.org/gitweb?a=blobdiff_plain;f=src%2Ftarget%2Farmv7a.h;h=663e5d92d14237eeca437fd5c6646e7da99ef0d7;hb=cfd79e96a6436cea427245a2c2f18fd52001898b;hp=ee0d2acb4b79bc2531fdddc7aa8041be5445155f;hpb=5949a3b3a55d987008b63b80af42c08601babb75;p=openocd.git

diff --git a/src/target/armv7a.h b/src/target/armv7a.h
index ee0d2acb4b..663e5d92d1 100644
--- a/src/target/armv7a.h
+++ b/src/target/armv7a.h
@@ -19,11 +19,11 @@
 #ifndef ARMV7A_H
 #define ARMV7A_H
 
-#include "arm_adi_v5.h"
-#include "armv4_5.h"
-#include "armv4_5_mmu.h"
-#include "armv4_5_cache.h"
-#include "arm_dpm.h"
+#include <target/arm_adi_v5.h>
+#include <target/arm.h>
+#include <target/armv4_5_mmu.h>
+#include <target/armv4_5_cache.h>
+#include <target/arm_dpm.h>
 
 enum
 {
@@ -77,21 +77,42 @@ target_to_armv7a(struct target *target)
 			armv4_5_common);
 }
 
-struct armv7a_algorithm
-{
-	int common_magic;
-
-	enum armv4_5_mode core_mode;
-	enum armv4_5_state core_state;
-};
-
-struct armv7a_core_reg
-{
-	int num;
-	enum armv4_5_mode mode;
-	struct target *target;
-	struct armv7a_common *armv7a_common;
-};
+/* register offsets from armv7a.debug_base */
+
+/* See ARMv7a arch spec section C10.2 */
+#define CPUDBG_DIDR		0x000
+
+/* See ARMv7a arch spec section C10.3 */
+#define CPUDBG_WFAR		0x018
+/* PCSR at 0x084 -or- 0x0a0 -or- both ... based on flags in DIDR */
+#define CPUDBG_DSCR		0x088
+#define CPUDBG_DRCR		0x090
+#define CPUDBG_PRCR		0x310
+#define CPUDBG_PRSR		0x314
+
+/* See ARMv7a arch spec section C10.4 */
+#define CPUDBG_DTRRX		0x080
+#define CPUDBG_ITR		0x084
+#define CPUDBG_DTRTX		0x08c
+
+/* See ARMv7a arch spec section C10.5 */
+#define CPUDBG_BVR_BASE		0x100
+#define CPUDBG_BCR_BASE		0x140
+#define CPUDBG_WVR_BASE		0x180
+#define CPUDBG_WCR_BASE		0x1C0
+#define CPUDBG_VCR		0x01C
+
+/* See ARMv7a arch spec section C10.6 */
+#define CPUDBG_OSLAR		0x300
+#define CPUDBG_OSLSR		0x304
+#define CPUDBG_OSSRR		0x308
+#define CPUDBG_ECR		0x024
+
+/* See ARMv7a arch spec section C10.7 */
+#define CPUDBG_DSCCR		0x028
+
+/* See ARMv7a arch spec section C10.8 */
+#define CPUDBG_AUTHSTATUS	0xFB8
 
 int armv7a_arch_state(struct target *target);
 struct reg_cache *armv7a_build_reg_cache(struct target *target,