X-Git-Url: https://review.openocd.org/gitweb?a=blobdiff_plain;f=src%2Ftarget%2Farmv7a.h;h=663e5d92d14237eeca437fd5c6646e7da99ef0d7;hb=cfd79e96a6436cea427245a2c2f18fd52001898b;hp=6ccf3e29821e62b3423014eac8a8163d4b0c06fd;hpb=1c7d3d200c6f20d4bb689176373368cd497d797f;p=openocd.git

diff --git a/src/target/armv7a.h b/src/target/armv7a.h
index 6ccf3e2982..663e5d92d1 100644
--- a/src/target/armv7a.h
+++ b/src/target/armv7a.h
@@ -19,11 +19,11 @@
 #ifndef ARMV7A_H
 #define ARMV7A_H
 
-#include "arm_adi_v5.h"
-#include "armv4_5.h"
-#include "armv4_5_mmu.h"
-#include "armv4_5_cache.h"
-#include "arm_dpm.h"
+#include <target/arm_adi_v5.h>
+#include <target/arm.h>
+#include <target/armv4_5_mmu.h>
+#include <target/armv4_5_cache.h>
+#include <target/arm_dpm.h>
 
 enum
 {
@@ -114,32 +114,6 @@ target_to_armv7a(struct target *target)
 /* See ARMv7a arch spec section C10.8 */
 #define CPUDBG_AUTHSTATUS	0xFB8
 
-/* DSCR bit numbers (See ARMv7a arch spec section 12.4.5) */
-#define DSCR_CORE_HALTED	0
-#define DSCR_CORE_RESTARTED	1
-#define DSCR_EXT_INT_EN		13
-#define DSCR_HALT_DBG_MODE	14
-#define DSCR_MON_DBG_MODE	15
-#define DSCR_INSTR_COMP		24
-#define DSCR_DTR_TX_FULL	29
-#define DSCR_DTR_RX_FULL	30
-
-struct armv7a_algorithm
-{
-	int common_magic;
-
-	enum armv4_5_mode core_mode;
-	enum armv4_5_state core_state;
-};
-
-struct armv7a_core_reg
-{
-	int num;
-	enum armv4_5_mode mode;
-	struct target *target;
-	struct armv7a_common *armv7a_common;
-};
-
 int armv7a_arch_state(struct target *target);
 struct reg_cache *armv7a_build_reg_cache(struct target *target,
 		struct armv7a_common *armv7a_common);