X-Git-Url: https://review.openocd.org/gitweb?a=blobdiff_plain;f=src%2Ftarget%2Farmv4_5.h;h=d76ce75920d79a78e86e434d5115adb401e4f27e;hb=ca594adb5a71f2bf60c1380172b8e61b075d9479;hp=aed3a48de318fbba8aea8826a9c726e111e40dc0;hpb=26b60a6ade45d048a9bfc70ff5d7ee58d4197f9d;p=openocd.git

diff --git a/src/target/armv4_5.h b/src/target/armv4_5.h
index aed3a48de3..d76ce75920 100644
--- a/src/target/armv4_5.h
+++ b/src/target/armv4_5.h
@@ -5,6 +5,9 @@
  *   Copyright (C) 2008 by Spencer Oliver                                  *
  *   spen@spen-soft.co.uk                                                  *
  *                                                                         *
+ *   Copyright (C) 2009 by Øyvind Harboe                                   *
+ *   oyvind.harboe@zylin.com                                               *
+ *                                                                         *
  *   This program is free software; you can redistribute it and/or modify  *
  *   it under the terms of the GNU General Public License as published by  *
  *   the Free Software Foundation; either version 2 of the License, or     *
@@ -74,14 +77,21 @@ typedef struct armv4_5_common_s
 {
 	int common_magic;
 	reg_cache_t *core_cache;
-	enum armv4_5_mode core_mode;
+	int /* armv4_5_mode */ core_mode;
 	enum armv4_5_state core_state;
+	bool is_armv4;
 	int (*full_context)(struct target_s *target);
 	int (*read_core_reg)(struct target_s *target, int num, enum armv4_5_mode mode);
 	int (*write_core_reg)(struct target_s *target, int num, enum armv4_5_mode mode, uint32_t value);
 	void *arch_info;
 } armv4_5_common_t;
 
+static inline struct armv4_5_common_s *
+target_to_armv4_5(struct target_s *target)
+{
+	return target->arch_info;
+}
+
 typedef struct armv4_5_algorithm_s
 {
 	int common_magic;
@@ -98,7 +108,8 @@ typedef struct armv4_5_core_reg_s
 	armv4_5_common_t *armv4_5_common;
 } armv4_5_core_reg_t;
 
-extern reg_cache_t* armv4_5_build_reg_cache(target_t *target, armv4_5_common_t *armv4_5_common);
+reg_cache_t* armv4_5_build_reg_cache(target_t *target,
+		armv4_5_common_t *armv4_5_common);
 
 /* map psr mode bits to linear number */
 static __inline int armv4_5_mode_to_number(enum armv4_5_mode mode)
@@ -137,15 +148,20 @@ static __inline enum armv4_5_mode armv4_5_number_to_mode(int number)
 	}
 };
 
-extern int armv4_5_arch_state(struct target_s *target);
-extern int armv4_5_get_gdb_reg_list(target_t *target, reg_t **reg_list[], int *reg_list_size);
+int armv4_5_arch_state(struct target_s *target);
+int armv4_5_get_gdb_reg_list(target_t *target,
+		reg_t **reg_list[], int *reg_list_size);
 
-extern int armv4_5_register_commands(struct command_context_s *cmd_ctx);
-extern int armv4_5_init_arch_info(target_t *target, armv4_5_common_t *armv4_5);
+int armv4_5_register_commands(struct command_context_s *cmd_ctx);
+int armv4_5_init_arch_info(target_t *target, armv4_5_common_t *armv4_5);
 
-extern int armv4_5_run_algorithm(struct target_s *target, int num_mem_params, mem_param_t *mem_params, int num_reg_params, reg_param_t *reg_params, uint32_t entry_point, uint32_t exit_point, int timeout_ms, void *arch_info);
+int armv4_5_run_algorithm(struct target_s *target,
+		int num_mem_params, mem_param_t *mem_params,
+		int num_reg_params, reg_param_t *reg_params,
+		uint32_t entry_point, uint32_t exit_point,
+		int timeout_ms, void *arch_info);
 
-extern int armv4_5_invalidate_core_regs(target_t *target);
+int armv4_5_invalidate_core_regs(target_t *target);
 
 /* ARM mode instructions
  */
@@ -314,4 +330,19 @@ extern int armv4_5_invalidate_core_regs(target_t *target);
  */
 #define ARMV5_T_BKPT(Im) ((0xbe00 | Im) | ((0xbe00 | Im) << 16))
 
+/* build basic mrc/mcr opcode */
+
+static inline uint32_t mrc_opcode(int cpnum, uint32_t op1, uint32_t op2, uint32_t CRn, uint32_t CRm)
+{
+	uint32_t t = 0;
+	t|=op1<<21;
+	t|=op2<<5;
+	t|=CRn<<16;
+	t|=CRm<<0;
+	return t;
+}
+
+
+
+
 #endif /* ARMV4_5_H */