X-Git-Url: https://review.openocd.org/gitweb?a=blobdiff_plain;f=src%2Ftarget%2Farmv4_5.h;h=b56a1f16eb2d57ef310ee55d8f03a365b8af3fde;hb=340e2eb7629fc1fdb6d2ead2952982584abdcefa;hp=e2b7b5a5c420819aed5e9e8a0454e904d983d9b5;hpb=d4d16f1036bff4ce3c36edd1995e579fbf64e1c9;p=openocd.git

diff --git a/src/target/armv4_5.h b/src/target/armv4_5.h
index e2b7b5a5c4..b56a1f16eb 100644
--- a/src/target/armv4_5.h
+++ b/src/target/armv4_5.h
@@ -30,8 +30,11 @@
 #include <helper/command.h>
 
 
-typedef enum arm_mode
-{
+/* These numbers match the five low bits of the *PSR registers on
+ * "classic ARM" processors, which build on the ARMv4 processor
+ * modes and register set.
+ */
+enum arm_mode {
 	ARM_MODE_USR = 16,
 	ARM_MODE_FIQ = 17,
 	ARM_MODE_IRQ = 18,
@@ -41,23 +44,28 @@ typedef enum arm_mode
 	ARM_MODE_UND = 27,
 	ARM_MODE_SYS = 31,
 	ARM_MODE_ANY = -1
-} arm_mode_t;
+};
 
 const char *arm_mode_name(unsigned psr_mode);
 bool is_arm_mode(unsigned psr_mode);
 
-int arm_mode_to_number(enum arm_mode mode);
-enum arm_mode armv4_5_number_to_mode(int number);
-
-typedef enum armv4_5_state
-{
+/* The PSR "T" and "J" bits define the mode of "classic ARM" cores */
+enum arm_state {
 	ARM_STATE_ARM,
 	ARM_STATE_THUMB,
 	ARM_STATE_JAZELLE,
 	ARM_STATE_THUMB_EE,
-} armv4_5_state_t;
+};
+
+extern const char *arm_state_strings[];
 
-extern char* armv4_5_state_strings[];
+/* OBSOLETE, DO NOT USE IN NEW CODE!  The "number" of an arm_mode is an
+ * index into the armv4_5_core_reg_map array.  Its remaining users are
+ * remnants which could as easily walk * the register cache directly as
+ * use the expensive ARMV4_5_CORE_REG_MODE() macro.
+ */
+int arm_mode_to_number(enum arm_mode mode);
+enum arm_mode armv4_5_number_to_mode(int number);
 
 extern const int armv4_5_core_reg_map[8][17];
 
@@ -67,7 +75,7 @@ extern const int armv4_5_core_reg_map[8][17];
 /* offset into armv4_5 core register cache -- OBSOLETE, DO NOT USE! */
 enum { ARMV4_5_CPSR = 31, };
 
-#define ARMV4_5_COMMON_MAGIC 0x0A450A45
+#define ARM_COMMON_MAGIC 0x0A450A45
 
 /**
  * Represents a generic ARM core, with standard application registers.
@@ -98,7 +106,7 @@ struct arm
 	enum arm_mode core_type;
 
 	enum arm_mode core_mode;
-	enum armv4_5_state core_state;
+	enum arm_state core_state;
 
 	/** Flag reporting unavailability of the BKPT instruction. */
 	bool is_armv4;
@@ -141,8 +149,6 @@ struct arm
 	void *arch_info;
 };
 
-#define target_to_armv4_5 target_to_arm
-
 /** Convert target handle to generic ARM target state handle. */
 static inline struct arm *target_to_arm(struct target *target)
 {
@@ -151,7 +157,7 @@ static inline struct arm *target_to_arm(struct target *target)
 
 static inline bool is_arm(struct arm *arm)
 {
-	return arm && arm->common_magic == ARMV4_5_COMMON_MAGIC;
+	return arm && arm->common_magic == ARM_COMMON_MAGIC;
 }
 
 struct armv4_5_algorithm
@@ -159,7 +165,7 @@ struct armv4_5_algorithm
 	int common_magic;
 
 	enum arm_mode core_mode;
-	enum armv4_5_state core_state;
+	enum arm_state core_state;
 };
 
 struct arm_reg