X-Git-Url: https://review.openocd.org/gitweb?a=blobdiff_plain;f=src%2Ftarget%2Farmv4_5.h;h=b56a1f16eb2d57ef310ee55d8f03a365b8af3fde;hb=340e2eb7629fc1fdb6d2ead2952982584abdcefa;hp=a9599c82ba97272622e46ce15afd2c71a41b415d;hpb=ff810723e051ed1f86cffcb565ade6b4d1fc50c8;p=openocd.git diff --git a/src/target/armv4_5.h b/src/target/armv4_5.h index a9599c82ba..b56a1f16eb 100644 --- a/src/target/armv4_5.h +++ b/src/target/armv4_5.h @@ -26,49 +26,56 @@ #ifndef ARMV4_5_H #define ARMV4_5_H -#include "target.h" +#include +#include -typedef enum armv4_5_mode -{ - ARMV4_5_MODE_USR = 16, - ARMV4_5_MODE_FIQ = 17, - ARMV4_5_MODE_IRQ = 18, - ARMV4_5_MODE_SVC = 19, - ARMV4_5_MODE_ABT = 23, + +/* These numbers match the five low bits of the *PSR registers on + * "classic ARM" processors, which build on the ARMv4 processor + * modes and register set. + */ +enum arm_mode { + ARM_MODE_USR = 16, + ARM_MODE_FIQ = 17, + ARM_MODE_IRQ = 18, + ARM_MODE_SVC = 19, + ARM_MODE_ABT = 23, ARM_MODE_MON = 26, - ARMV4_5_MODE_UND = 27, - ARMV4_5_MODE_SYS = 31, - ARMV4_5_MODE_ANY = -1 -} armv4_5_mode_t; + ARM_MODE_UND = 27, + ARM_MODE_SYS = 31, + ARM_MODE_ANY = -1 +}; const char *arm_mode_name(unsigned psr_mode); bool is_arm_mode(unsigned psr_mode); -int armv4_5_mode_to_number(enum armv4_5_mode mode); -enum armv4_5_mode armv4_5_number_to_mode(int number); - -typedef enum armv4_5_state -{ - ARMV4_5_STATE_ARM, - ARMV4_5_STATE_THUMB, - ARMV4_5_STATE_JAZELLE, +/* The PSR "T" and "J" bits define the mode of "classic ARM" cores */ +enum arm_state { + ARM_STATE_ARM, + ARM_STATE_THUMB, + ARM_STATE_JAZELLE, ARM_STATE_THUMB_EE, -} armv4_5_state_t; +}; + +extern const char *arm_state_strings[]; -extern char* armv4_5_state_strings[]; +/* OBSOLETE, DO NOT USE IN NEW CODE! The "number" of an arm_mode is an + * index into the armv4_5_core_reg_map array. Its remaining users are + * remnants which could as easily walk * the register cache directly as + * use the expensive ARMV4_5_CORE_REG_MODE() macro. + */ +int arm_mode_to_number(enum arm_mode mode); +enum arm_mode armv4_5_number_to_mode(int number); extern const int armv4_5_core_reg_map[8][17]; #define ARMV4_5_CORE_REG_MODE(cache, mode, num) \ - cache->reg_list[armv4_5_core_reg_map[armv4_5_mode_to_number(mode)][num]] + cache->reg_list[armv4_5_core_reg_map[arm_mode_to_number(mode)][num]] /* offset into armv4_5 core register cache -- OBSOLETE, DO NOT USE! */ enum { ARMV4_5_CPSR = 31, }; -#define ARMV4_5_COMMON_MAGIC 0x0A450A45 - -/* NOTE: this is being morphed into a generic toplevel holder for ARMs. */ -#define armv4_5_common_s arm +#define ARM_COMMON_MAGIC 0x0A450A45 /** * Represents a generic ARM core, with standard application registers. @@ -92,31 +99,56 @@ struct arm /** * Indicates what registers are in the ARM state core register set. - * ARMV4_5_MODE_ANY indicates the standard set of 37 registers, + * ARM_MODE_ANY indicates the standard set of 37 registers, * seen on for example ARM7TDMI cores. ARM_MODE_MON indicates three * more registers are shadowed, for "Secure Monitor" mode. */ - enum armv4_5_mode core_type; + enum arm_mode core_type; - enum armv4_5_mode core_mode; - enum armv4_5_state core_state; + enum arm_mode core_mode; + enum arm_state core_state; /** Flag reporting unavailability of the BKPT instruction. */ bool is_armv4; + /** Flag reporting whether semihosting is active. */ + bool is_semihosting; + + /** Value to be returned by semihosting SYS_ERRNO request. */ + int semihosting_errno; + + /** Backpointer to the target. */ + struct target *target; + + /** Handle for the debug module, if one is present. */ + struct arm_dpm *dpm; + /** Handle for the Embedded Trace Module, if one is present. */ struct etm_context *etm; + /* FIXME all these methods should take "struct arm *" not target */ + int (*full_context)(struct target *target); int (*read_core_reg)(struct target *target, struct reg *reg, - int num, enum armv4_5_mode mode); + int num, enum arm_mode mode); int (*write_core_reg)(struct target *target, struct reg *reg, - int num, enum armv4_5_mode mode, uint32_t value); + int num, enum arm_mode mode, uint32_t value); + + /** Read coprocessor register. */ + int (*mrc)(struct target *target, int cpnum, + uint32_t op1, uint32_t op2, + uint32_t CRn, uint32_t CRm, + uint32_t *value); + + /* Write coprocessor register. */ + int (*mcr)(struct target *target, int cpnum, + uint32_t op1, uint32_t op2, + uint32_t CRn, uint32_t CRm, + uint32_t value); + void *arch_info; }; -#define target_to_armv4_5 target_to_arm - /** Convert target handle to generic ARM target state handle. */ static inline struct arm *target_to_arm(struct target *target) { @@ -125,21 +157,21 @@ static inline struct arm *target_to_arm(struct target *target) static inline bool is_arm(struct arm *arm) { - return arm && arm->common_magic == ARMV4_5_COMMON_MAGIC; + return arm && arm->common_magic == ARM_COMMON_MAGIC; } struct armv4_5_algorithm { int common_magic; - enum armv4_5_mode core_mode; - enum armv4_5_state core_state; + enum arm_mode core_mode; + enum arm_state core_state; }; struct arm_reg { int num; - enum armv4_5_mode mode; + enum arm_mode mode; struct target *target; struct arm *armv4_5_common; uint32_t value; @@ -152,7 +184,8 @@ int armv4_5_arch_state(struct target *target); int armv4_5_get_gdb_reg_list(struct target *target, struct reg **reg_list[], int *reg_list_size); -int armv4_5_register_commands(struct command_context *cmd_ctx); +extern const struct command_registration arm_command_handlers[]; + int armv4_5_init_arch_info(struct target *target, struct arm *armv4_5); int armv4_5_run_algorithm(struct target *target,