X-Git-Url: https://review.openocd.org/gitweb?a=blobdiff_plain;f=src%2Ftarget%2Farmv4_5.h;h=b56a1f16eb2d57ef310ee55d8f03a365b8af3fde;hb=340e2eb7629fc1fdb6d2ead2952982584abdcefa;hp=3868fa3847b44f3c622c0051bf1719e52522af07;hpb=454b0a65e6addf87c12da37bb4121d330aec262c;p=openocd.git diff --git a/src/target/armv4_5.h b/src/target/armv4_5.h index 3868fa3847..b56a1f16eb 100644 --- a/src/target/armv4_5.h +++ b/src/target/armv4_5.h @@ -2,6 +2,12 @@ * Copyright (C) 2005 by Dominic Rath * * Dominic.Rath@gmx.de * * * + * Copyright (C) 2008 by Spencer Oliver * + * spen@spen-soft.co.uk * + * * + * Copyright (C) 2009 by Øyvind Harboe * + * oyvind.harboe@zylin.com * + * * * This program is free software; you can redistribute it and/or modify * * it under the terms of the GNU General Public License as published by * * the Free Software Foundation; either version 2 of the License, or * @@ -20,140 +26,193 @@ #ifndef ARMV4_5_H #define ARMV4_5_H -#include "register.h" -#include "target.h" -#include "log.h" +#include +#include -typedef enum armv4_5_mode -{ - ARMV4_5_MODE_USR = 16, - ARMV4_5_MODE_FIQ = 17, - ARMV4_5_MODE_IRQ = 18, - ARMV4_5_MODE_SVC = 19, - ARMV4_5_MODE_ABT = 23, - ARMV4_5_MODE_UND = 27, - ARMV4_5_MODE_SYS = 31, - ARMV4_5_MODE_ANY = -1 -} armv4_5_mode_t; - -extern char** armv4_5_mode_strings; - -typedef enum armv4_5_state -{ - ARMV4_5_STATE_ARM, - ARMV4_5_STATE_THUMB, - ARMV4_5_STATE_JAZELLE, -} armv4_5_state_t; -extern char* armv4_5_state_strings[]; +/* These numbers match the five low bits of the *PSR registers on + * "classic ARM" processors, which build on the ARMv4 processor + * modes and register set. + */ +enum arm_mode { + ARM_MODE_USR = 16, + ARM_MODE_FIQ = 17, + ARM_MODE_IRQ = 18, + ARM_MODE_SVC = 19, + ARM_MODE_ABT = 23, + ARM_MODE_MON = 26, + ARM_MODE_UND = 27, + ARM_MODE_SYS = 31, + ARM_MODE_ANY = -1 +}; + +const char *arm_mode_name(unsigned psr_mode); +bool is_arm_mode(unsigned psr_mode); -extern int armv4_5_core_reg_map[7][17]; +/* The PSR "T" and "J" bits define the mode of "classic ARM" cores */ +enum arm_state { + ARM_STATE_ARM, + ARM_STATE_THUMB, + ARM_STATE_JAZELLE, + ARM_STATE_THUMB_EE, +}; + +extern const char *arm_state_strings[]; + +/* OBSOLETE, DO NOT USE IN NEW CODE! The "number" of an arm_mode is an + * index into the armv4_5_core_reg_map array. Its remaining users are + * remnants which could as easily walk * the register cache directly as + * use the expensive ARMV4_5_CORE_REG_MODE() macro. + */ +int arm_mode_to_number(enum arm_mode mode); +enum arm_mode armv4_5_number_to_mode(int number); + +extern const int armv4_5_core_reg_map[8][17]; #define ARMV4_5_CORE_REG_MODE(cache, mode, num) \ - cache->reg_list[armv4_5_core_reg_map[armv4_5_mode_to_number(mode)][num]] -#define ARMV4_5_CORE_REG_MODENUM(cache, mode, num) \ - cache->reg_list[armv4_5_core_reg_map[mode][num]] + cache->reg_list[armv4_5_core_reg_map[arm_mode_to_number(mode)][num]] -/* offsets into armv4_5 core register cache */ -enum -{ - ARMV4_5_CPSR = 31, - ARMV4_5_SPSR_FIQ = 32, - ARMV4_5_SPSR_IRQ = 33, - ARMV4_5_SPSR_SVC = 34, - ARMV4_5_SPSR_ABT = 35, - ARMV4_5_SPSR_UND = 36 -}; +/* offset into armv4_5 core register cache -- OBSOLETE, DO NOT USE! */ +enum { ARMV4_5_CPSR = 31, }; -#define ARMV4_5_COMMON_MAGIC 0x0A450A45 +#define ARM_COMMON_MAGIC 0x0A450A45 -typedef struct armv4_5_common_s +/** + * Represents a generic ARM core, with standard application registers. + * + * There are sixteen application registers (including PC, SP, LR) and a PSR. + * Cortex-M series cores do not support as many core states or shadowed + * registers as traditional ARM cores, and only support Thumb2 instructions. + */ +struct arm { int common_magic; - reg_cache_t *core_cache; - enum armv4_5_mode core_mode; - enum armv4_5_state core_state; - int (*full_context)(struct target_s *target); - int (*read_core_reg)(struct target_s *target, int num, enum armv4_5_mode mode); - int (*write_core_reg)(struct target_s *target, int num, enum armv4_5_mode mode, u32 value); + struct reg_cache *core_cache; + + /** Handle to the CPSR; valid in all core modes. */ + struct reg *cpsr; + + /** Handle to the SPSR; valid only in core modes with an SPSR. */ + struct reg *spsr; + + const int *map; + + /** + * Indicates what registers are in the ARM state core register set. + * ARM_MODE_ANY indicates the standard set of 37 registers, + * seen on for example ARM7TDMI cores. ARM_MODE_MON indicates three + * more registers are shadowed, for "Secure Monitor" mode. + */ + enum arm_mode core_type; + + enum arm_mode core_mode; + enum arm_state core_state; + + /** Flag reporting unavailability of the BKPT instruction. */ + bool is_armv4; + + /** Flag reporting whether semihosting is active. */ + bool is_semihosting; + + /** Value to be returned by semihosting SYS_ERRNO request. */ + int semihosting_errno; + + /** Backpointer to the target. */ + struct target *target; + + /** Handle for the debug module, if one is present. */ + struct arm_dpm *dpm; + + /** Handle for the Embedded Trace Module, if one is present. */ + struct etm_context *etm; + + /* FIXME all these methods should take "struct arm *" not target */ + + int (*full_context)(struct target *target); + int (*read_core_reg)(struct target *target, struct reg *reg, + int num, enum arm_mode mode); + int (*write_core_reg)(struct target *target, struct reg *reg, + int num, enum arm_mode mode, uint32_t value); + + /** Read coprocessor register. */ + int (*mrc)(struct target *target, int cpnum, + uint32_t op1, uint32_t op2, + uint32_t CRn, uint32_t CRm, + uint32_t *value); + + /* Write coprocessor register. */ + int (*mcr)(struct target *target, int cpnum, + uint32_t op1, uint32_t op2, + uint32_t CRn, uint32_t CRm, + uint32_t value); + void *arch_info; -} armv4_5_common_t; +}; -typedef struct armv4_5_algorithm_s +/** Convert target handle to generic ARM target state handle. */ +static inline struct arm *target_to_arm(struct target *target) { - int common_magic; - - enum armv4_5_mode core_mode; - enum armv4_5_state core_state; -} armv4_5_algorithm_t; + return target->arch_info; +} -typedef struct armv4_5_core_reg_s +static inline bool is_arm(struct arm *arm) { - int num; - enum armv4_5_mode mode; - target_t *target; - armv4_5_common_t *armv4_5_common; -} armv4_5_core_reg_t; - -extern reg_cache_t* armv4_5_build_reg_cache(target_t *target, armv4_5_common_t *armv4_5_common); + return arm && arm->common_magic == ARM_COMMON_MAGIC; +} -/* map psr mode bits to linear number */ -static __inline int armv4_5_mode_to_number(enum armv4_5_mode mode) +struct armv4_5_algorithm { - switch (mode) - { - case ARMV4_5_MODE_USR: return 0; break; - case ARMV4_5_MODE_FIQ: return 1; break; - case ARMV4_5_MODE_IRQ: return 2; break; - case ARMV4_5_MODE_SVC: return 3; break; - case ARMV4_5_MODE_ABT: return 4; break; - case ARMV4_5_MODE_UND: return 5; break; - case ARMV4_5_MODE_SYS: return 6; break; - case ARMV4_5_MODE_ANY: return 0; break; /* map MODE_ANY to user mode */ - default: - LOG_ERROR("invalid mode value encountered"); - return -1; - } -} + int common_magic; + + enum arm_mode core_mode; + enum arm_state core_state; +}; -/* map linear number to mode bits */ -static __inline enum armv4_5_mode armv4_5_number_to_mode(int number) +struct arm_reg { - switch(number) - { - case 0: return ARMV4_5_MODE_USR; break; - case 1: return ARMV4_5_MODE_FIQ; break; - case 2: return ARMV4_5_MODE_IRQ; break; - case 3: return ARMV4_5_MODE_SVC; break; - case 4: return ARMV4_5_MODE_ABT; break; - case 5: return ARMV4_5_MODE_UND; break; - case 6: return ARMV4_5_MODE_SYS; break; - default: - LOG_ERROR("mode index out of bounds"); - return -1; - } + int num; + enum arm_mode mode; + struct target *target; + struct arm *armv4_5_common; + uint32_t value; }; +struct reg_cache* armv4_5_build_reg_cache(struct target *target, + struct arm *armv4_5_common); + +int armv4_5_arch_state(struct target *target); +int armv4_5_get_gdb_reg_list(struct target *target, + struct reg **reg_list[], int *reg_list_size); + +extern const struct command_registration arm_command_handlers[]; -extern int armv4_5_arch_state(struct target_s *target); -extern int armv4_5_get_gdb_reg_list(target_t *target, reg_t **reg_list[], int *reg_list_size); -extern int armv4_5_invalidate_core_regs(target_t *target); +int armv4_5_init_arch_info(struct target *target, struct arm *armv4_5); -extern int armv4_5_register_commands(struct command_context_s *cmd_ctx); -extern int armv4_5_init_arch_info(target_t *target, armv4_5_common_t *armv4_5); +int armv4_5_run_algorithm(struct target *target, + int num_mem_params, struct mem_param *mem_params, + int num_reg_params, struct reg_param *reg_params, + uint32_t entry_point, uint32_t exit_point, + int timeout_ms, void *arch_info); -extern int armv4_5_run_algorithm(struct target_s *target, int num_mem_params, mem_param_t *mem_params, int num_reg_params, reg_param_t *reg_params, u32 entry_point, u32 exit_point, int timeout_ms, void *arch_info); +int arm_checksum_memory(struct target *target, + uint32_t address, uint32_t count, uint32_t *checksum); +int arm_blank_check_memory(struct target *target, + uint32_t address, uint32_t count, uint32_t *blank); -extern int armv4_5_invalidate_core_regs(target_t *target); +void arm_set_cpsr(struct arm *arm, uint32_t cpsr); +struct reg *arm_reg_current(struct arm *arm, unsigned regnum); + +extern struct reg arm_gdb_dummy_fp_reg; +extern struct reg arm_gdb_dummy_fps_reg; /* ARM mode instructions */ - + /* Store multiple increment after * Rn: base register * List: for each bit in list: store register * S: in priviledged mode: store user-mode registers - * W=1: update the base register. W=0: leave the base register untouched + * W = 1: update the base register. W = 0: leave the base register untouched */ #define ARMV4_5_STMIA(Rn, List, S, W) (0xe8800000 | ((S) << 22) | ((W) << 21) | ((Rn) << 16) | (List)) @@ -161,7 +220,7 @@ extern int armv4_5_invalidate_core_regs(target_t *target); * Rn: base register * List: for each bit in list: store register * S: in priviledged mode: store user-mode registers - * W=1: update the base register. W=0: leave the base register untouched + * W = 1: update the base register. W = 0: leave the base register untouched */ #define ARMV4_5_LDMIA(Rn, List, S, W) (0xe8900000 | ((S) << 22) | ((W) << 21) | ((Rn) << 16) | (List)) @@ -169,7 +228,7 @@ extern int armv4_5_invalidate_core_regs(target_t *target); #define ARMV4_5_NOP (0xe1a08008) /* Move PSR to general purpose register - * R=1: SPSR R=0: CPSR + * R = 1: SPSR R = 0: CPSR * Rn: target register */ #define ARMV4_5_MRS(Rn, R) (0xe10f0000 | ((R) << 22) | ((Rn) << 12)) @@ -187,7 +246,7 @@ extern int armv4_5_invalidate_core_regs(target_t *target); #define ARMV4_5_LDR(Rd, Rn) (0xe5900000 | ((Rd) << 12) | ((Rn) << 16)) /* Move general purpose register to PSR - * R=1: SPSR R=0: CPSR + * R = 1: SPSR R = 0: CPSR * Field: Field mask * 1: control field 2: extension field 4: status field 8: flags field * Rm: source register @@ -238,7 +297,7 @@ extern int armv4_5_invalidate_core_regs(target_t *target); * CRm: second coprocessor operand * op2: Second coprocessor opcode */ -#define ARMV4_5_MRC(CP, op1, Rd, CRn, CRm, op2) (0xee100010 | (CRm) | ((op2) << 5) | ((CP) << 8) | ((Rd) << 12) | ((CRn) << 16) | ((op1) << 21)) +#define ARMV4_5_MRC(CP, op1, Rd, CRn, CRm, op2) (0xee100010 | (CRm) | ((op2) << 5) | ((CP) << 8) | ((Rd) << 12) | ((CRn) << 16) | ((op1) << 21)) /* Move to coprocessor from ARM register * CP: Coprocessor number @@ -248,7 +307,7 @@ extern int armv4_5_invalidate_core_regs(target_t *target); * CRm: second coprocessor operand * op2: Second coprocessor opcode */ -#define ARMV4_5_MCR(CP, op1, Rd, CRn, CRm, op2) (0xee000010 | (CRm) | ((op2) << 5) | ((CP) << 8) | ((Rd) << 12) | ((CRn) << 16) | ((op1) << 21)) +#define ARMV4_5_MCR(CP, op1, Rd, CRn, CRm, op2) (0xee000010 | (CRm) | ((op2) << 5) | ((CP) << 8) | ((Rd) << 12) | ((CRn) << 16) | ((op1) << 21)) /* Breakpoint instruction (ARMv5) * Im: 16-bit immediate @@ -258,7 +317,7 @@ extern int armv4_5_invalidate_core_regs(target_t *target); /* Thumb mode instructions */ - + /* Store register (Thumb mode) * Rd: source register * Rn: base register @@ -276,12 +335,12 @@ extern int armv4_5_invalidate_core_regs(target_t *target); * List: for each bit in list: store register */ #define ARMV4_5_T_LDMIA(Rn, List) ((0xc800 | ((Rn) << 8) | (List)) | ((0xc800 | ((Rn) << 8) | List) << 16)) - + /* Load register with PC relative addressing * Rd: register to load */ -#define ARMV4_5_T_LDR_PCREL(Rd) ((0x4800 | ((Rd) << 8)) | ((0x4800 | ((Rd) << 8)) << 16)) - +#define ARMV4_5_T_LDR_PCREL(Rd) ((0x4800 | ((Rd) << 8)) | ((0x4800 | ((Rd) << 8)) << 16)) + /* Move hi register (Thumb mode) * Rd: destination register * Rm: source register @@ -313,4 +372,16 @@ extern int armv4_5_invalidate_core_regs(target_t *target); */ #define ARMV5_T_BKPT(Im) ((0xbe00 | Im) | ((0xbe00 | Im) << 16)) +/* build basic mrc/mcr opcode */ + +static inline uint32_t mrc_opcode(int cpnum, uint32_t op1, uint32_t op2, uint32_t CRn, uint32_t CRm) +{ + uint32_t t = 0; + t|=op1<<21; + t|=op2<<5; + t|=CRn<<16; + t|=CRm<<0; + return t; +} + #endif /* ARMV4_5_H */