X-Git-Url: https://review.openocd.org/gitweb?a=blobdiff_plain;f=src%2Ftarget%2Farmv4_5.c;h=c7b73676aff7ce906839d66508b86c7bb7004d9c;hb=fb71a0a0dddf68fa3f266aab5e35409773acc567;hp=15c0a7f47f6c761aba0e759c05a4c46109d10437;hpb=d4d16f1036bff4ce3c36edd1995e579fbf64e1c9;p=openocd.git

diff --git a/src/target/armv4_5.c b/src/target/armv4_5.c
index 15c0a7f47f..c7b73676af 100644
--- a/src/target/armv4_5.c
+++ b/src/target/armv4_5.c
@@ -27,6 +27,7 @@
 #include "config.h"
 #endif
 
+#include "arm.h"
 #include "armv4_5.h"
 #include "arm_jtag.h"
 #include "breakpoints.h"
@@ -216,7 +217,7 @@ enum arm_mode armv4_5_number_to_mode(int number)
 	}
 }
 
-char* armv4_5_state_strings[] =
+const char *arm_state_strings[] =
 {
 	"ARM", "Thumb", "Jazelle", "ThumbEE",
 };
@@ -374,7 +375,7 @@ void arm_set_cpsr(struct arm *arm, uint32_t cpsr)
 			: arm->core_cache->reg_list + arm->map[16];
 
 	/* Older ARMs won't have the J bit */
-	enum armv4_5_state state;
+	enum arm_state state;
 
 	if (cpsr & (1 << 5)) {	/* T */
 		if (cpsr & (1 << 24)) {	/* J */
@@ -393,7 +394,7 @@ void arm_set_cpsr(struct arm *arm, uint32_t cpsr)
 
 	LOG_DEBUG("set CPSR %#8.8x: %s mode, %s state", (unsigned) cpsr,
 			arm_mode_name(mode),
-			armv4_5_state_strings[arm->core_state]);
+			arm_state_strings[arm->core_state]);
 }
 
 /**
@@ -491,7 +492,7 @@ static int armv4_5_set_core_reg(struct reg *reg, uint8_t *buf)
 {
 	struct arm_reg *armv4_5 = reg->arch_info;
 	struct target *target = armv4_5->target;
-	struct arm *armv4_5_target = target_to_armv4_5(target);
+	struct arm *armv4_5_target = target_to_arm(target);
 	uint32_t value = buf_get_u32(buf, 0, 32);
 
 	if (target->state != TARGET_HALTED)
@@ -533,7 +534,7 @@ static const struct reg_arch_type arm_reg_type = {
 	.set = armv4_5_set_core_reg,
 };
 
-struct reg_cache* armv4_5_build_reg_cache(struct target *target, struct arm *armv4_5_common)
+struct reg_cache *arm_build_reg_cache(struct target *target, struct arm *arm)
 {
 	int num_regs = ARRAY_SIZE(arm_core_regs);
 	struct reg_cache *cache = malloc(sizeof(struct reg_cache));
@@ -557,7 +558,7 @@ struct reg_cache* armv4_5_build_reg_cache(struct target *target, struct arm *arm
 	{
 		/* Skip registers this core doesn't expose */
 		if (arm_core_regs[i].mode == ARM_MODE_MON
-				&& armv4_5_common->core_type != ARM_MODE_MON)
+				&& arm->core_type != ARM_MODE_MON)
 			continue;
 
 		/* REVISIT handle Cortex-M, which only shadows R13/SP */
@@ -565,7 +566,7 @@ struct reg_cache* armv4_5_build_reg_cache(struct target *target, struct arm *arm
 		arch_info[i].num = arm_core_regs[i].cookie;
 		arch_info[i].mode = arm_core_regs[i].mode;
 		arch_info[i].target = target;
-		arch_info[i].armv4_5_common = armv4_5_common;
+		arch_info[i].armv4_5_common = arm;
 
 		reg_list[i].name = (char *) arm_core_regs[i].name;
 		reg_list[i].size = 32;
@@ -576,16 +577,16 @@ struct reg_cache* armv4_5_build_reg_cache(struct target *target, struct arm *arm
 		cache->num_regs++;
 	}
 
-	armv4_5_common->cpsr = reg_list + ARMV4_5_CPSR;
-	armv4_5_common->core_cache = cache;
+	arm->cpsr = reg_list + ARMV4_5_CPSR;
+	arm->core_cache = cache;
 	return cache;
 }
 
-int armv4_5_arch_state(struct target *target)
+int arm_arch_state(struct target *target)
 {
-	struct arm *armv4_5 = target_to_armv4_5(target);
+	struct arm *armv4_5 = target_to_arm(target);
 
-	if (armv4_5->common_magic != ARMV4_5_COMMON_MAGIC)
+	if (armv4_5->common_magic != ARM_COMMON_MAGIC)
 	{
 		LOG_ERROR("BUG: called for a non-ARM target");
 		return ERROR_FAIL;
@@ -593,11 +594,10 @@ int armv4_5_arch_state(struct target *target)
 
 	LOG_USER("target halted in %s state due to %s, current mode: %s\n"
 			"cpsr: 0x%8.8" PRIx32 " pc: 0x%8.8" PRIx32 "%s",
-			 armv4_5_state_strings[armv4_5->core_state],
-			 Jim_Nvp_value2name_simple(nvp_target_debug_reason,
-					target->debug_reason)->name,
-			 arm_mode_name(armv4_5->core_mode),
-			 buf_get_u32(armv4_5->cpsr->value, 0, 32),
+			arm_state_strings[armv4_5->core_state],
+			debug_reason_name(target),
+			arm_mode_name(armv4_5->core_mode),
+			buf_get_u32(armv4_5->cpsr->value, 0, 32),
 			buf_get_u32(armv4_5->core_cache->reg_list[15].value,
 					0, 32),
 			armv4_5->is_semihosting ? ", semihosting" : "");
@@ -611,7 +611,7 @@ int armv4_5_arch_state(struct target *target)
 COMMAND_HANDLER(handle_armv4_5_reg_command)
 {
 	struct target *target = get_current_target(CMD_CTX);
-	struct arm *armv4_5 = target_to_armv4_5(target);
+	struct arm *armv4_5 = target_to_arm(target);
 	unsigned num_regs;
 	struct reg *regs;
 
@@ -698,7 +698,7 @@ COMMAND_HANDLER(handle_armv4_5_reg_command)
 COMMAND_HANDLER(handle_armv4_5_core_state_command)
 {
 	struct target *target = get_current_target(CMD_CTX);
-	struct arm *armv4_5 = target_to_armv4_5(target);
+	struct arm *armv4_5 = target_to_arm(target);
 
 	if (!is_arm(armv4_5))
 	{
@@ -718,7 +718,7 @@ COMMAND_HANDLER(handle_armv4_5_core_state_command)
 		}
 	}
 
-	command_print(CMD_CTX, "core state: %s", armv4_5_state_strings[armv4_5->core_state]);
+	command_print(CMD_CTX, "core state: %s", arm_state_strings[armv4_5->core_state]);
 
 	return ERROR_OK;
 }
@@ -928,22 +928,22 @@ static int jim_mcrmrc(Jim_Interp *interp, int argc, Jim_Obj *const *argv)
 static const struct command_registration arm_exec_command_handlers[] = {
 	{
 		.name = "reg",
-		.handler = &handle_armv4_5_reg_command,
+		.handler = handle_armv4_5_reg_command,
 		.mode = COMMAND_EXEC,
 		.help = "display ARM core registers",
 	},
 	{
 		.name = "core_state",
-		.handler = &handle_armv4_5_core_state_command,
+		.handler = handle_armv4_5_core_state_command,
 		.mode = COMMAND_EXEC,
-		.usage = "<arm | thumb>",
+		.usage = "['arm'|'thumb']",
 		.help = "display/change ARM core state",
 	},
 	{
 		.name = "disassemble",
-		.handler = &handle_armv4_5_disassemble_command,
+		.handler = handle_armv4_5_disassemble_command,
 		.mode = COMMAND_EXEC,
-		.usage = "<address> [<count> ['thumb']]",
+		.usage = "address [count ['thumb']]",
 		.help = "disassemble instructions ",
 	},
 	{
@@ -972,9 +972,10 @@ const struct command_registration arm_command_handlers[] = {
 	COMMAND_REGISTRATION_DONE
 };
 
-int armv4_5_get_gdb_reg_list(struct target *target, struct reg **reg_list[], int *reg_list_size)
+int arm_get_gdb_reg_list(struct target *target,
+		struct reg **reg_list[], int *reg_list_size)
 {
-	struct arm *armv4_5 = target_to_armv4_5(target);
+	struct arm *armv4_5 = target_to_arm(target);
 	int i;
 
 	if (!is_arm_mode(armv4_5->core_mode))
@@ -999,7 +1000,7 @@ int armv4_5_get_gdb_reg_list(struct target *target, struct reg **reg_list[], int
 static int armv4_5_run_algorithm_completion(struct target *target, uint32_t exit_point, int timeout_ms, void *arch_info)
 {
 	int retval;
-	struct arm *armv4_5 = target_to_armv4_5(target);
+	struct arm *armv4_5 = target_to_arm(target);
 
 	if ((retval = target_wait_state(target, TARGET_HALTED, timeout_ms)) != ERROR_OK)
 	{
@@ -1036,9 +1037,9 @@ int armv4_5_run_algorithm_inner(struct target *target,
 		int (*run_it)(struct target *target, uint32_t exit_point,
 				int timeout_ms, void *arch_info))
 {
-	struct arm *armv4_5 = target_to_armv4_5(target);
-	struct armv4_5_algorithm *armv4_5_algorithm_info = arch_info;
-	enum armv4_5_state core_state = armv4_5->core_state;
+	struct arm *armv4_5 = target_to_arm(target);
+	struct arm_algorithm *arm_algorithm_info = arch_info;
+	enum arm_state core_state = armv4_5->core_state;
 	uint32_t context[17];
 	uint32_t cpsr;
 	int exit_breakpoint_size = 0;
@@ -1047,7 +1048,7 @@ int armv4_5_run_algorithm_inner(struct target *target,
 
 	LOG_DEBUG("Running algorithm");
 
-	if (armv4_5_algorithm_info->common_magic != ARMV4_5_COMMON_MAGIC)
+	if (arm_algorithm_info->common_magic != ARM_COMMON_MAGIC)
 	{
 		LOG_ERROR("current target isn't an ARMV4/5 target");
 		return ERROR_TARGET_INVALID;
@@ -1077,10 +1078,10 @@ int armv4_5_run_algorithm_inner(struct target *target,
 		struct reg *r;
 
 		r = &ARMV4_5_CORE_REG_MODE(armv4_5->core_cache,
-				armv4_5_algorithm_info->core_mode, i);
+				arm_algorithm_info->core_mode, i);
 		if (!r->valid)
 			armv4_5->read_core_reg(target, r, i,
-					armv4_5_algorithm_info->core_mode);
+					arm_algorithm_info->core_mode);
 		context[i] = buf_get_u32(r->value, 0, 32);
 	}
 	cpsr = buf_get_u32(armv4_5->cpsr->value, 0, 32);
@@ -1114,7 +1115,7 @@ int armv4_5_run_algorithm_inner(struct target *target,
 		}
 	}
 
-	armv4_5->core_state = armv4_5_algorithm_info->core_state;
+	armv4_5->core_state = arm_algorithm_info->core_state;
 	if (armv4_5->core_state == ARM_STATE_ARM)
 		exit_breakpoint_size = 4;
 	else if (armv4_5->core_state == ARM_STATE_THUMB)
@@ -1125,12 +1126,12 @@ int armv4_5_run_algorithm_inner(struct target *target,
 		return ERROR_INVALID_ARGUMENTS;
 	}
 
-	if (armv4_5_algorithm_info->core_mode != ARM_MODE_ANY)
+	if (arm_algorithm_info->core_mode != ARM_MODE_ANY)
 	{
 		LOG_DEBUG("setting core_mode: 0x%2.2x",
-				armv4_5_algorithm_info->core_mode);
+				arm_algorithm_info->core_mode);
 		buf_set_u32(armv4_5->cpsr->value, 0, 5,
-				armv4_5_algorithm_info->core_mode);
+				arm_algorithm_info->core_mode);
 		armv4_5->cpsr->dirty = 1;
 		armv4_5->cpsr->valid = 1;
 	}
@@ -1193,13 +1194,13 @@ int armv4_5_run_algorithm_inner(struct target *target,
 	for (i = 0; i <= 16; i++)
 	{
 		uint32_t regvalue;
-		regvalue = buf_get_u32(ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_algorithm_info->core_mode, i).value, 0, 32);
+		regvalue = buf_get_u32(ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, arm_algorithm_info->core_mode, i).value, 0, 32);
 		if (regvalue != context[i])
 		{
-			LOG_DEBUG("restoring register %s with value 0x%8.8" PRIx32 "", ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_algorithm_info->core_mode, i).name, context[i]);
-			buf_set_u32(ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_algorithm_info->core_mode, i).value, 0, 32, context[i]);
-			ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_algorithm_info->core_mode, i).valid = 1;
-			ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_algorithm_info->core_mode, i).dirty = 1;
+			LOG_DEBUG("restoring register %s with value 0x%8.8" PRIx32 "", ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, arm_algorithm_info->core_mode, i).name, context[i]);
+			buf_set_u32(ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, arm_algorithm_info->core_mode, i).value, 0, 32, context[i]);
+			ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, arm_algorithm_info->core_mode, i).valid = 1;
+			ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, arm_algorithm_info->core_mode, i).dirty = 1;
 		}
 	}
 
@@ -1225,7 +1226,7 @@ int arm_checksum_memory(struct target *target,
 		uint32_t address, uint32_t count, uint32_t *checksum)
 {
 	struct working_area *crc_algorithm;
-	struct armv4_5_algorithm armv4_5_info;
+	struct arm_algorithm armv4_5_info;
 	struct reg_param reg_params[2];
 	int retval;
 	uint32_t i;
@@ -1273,7 +1274,7 @@ int arm_checksum_memory(struct target *target,
 			return retval;
 	}
 
-	armv4_5_info.common_magic = ARMV4_5_COMMON_MAGIC;
+	armv4_5_info.common_magic = ARM_COMMON_MAGIC;
 	armv4_5_info.core_mode = ARM_MODE_SVC;
 	armv4_5_info.core_state = ARM_STATE_ARM;
 
@@ -1320,7 +1321,7 @@ int arm_blank_check_memory(struct target *target,
 {
 	struct working_area *check_algorithm;
 	struct reg_param reg_params[3];
-	struct armv4_5_algorithm armv4_5_info;
+	struct arm_algorithm armv4_5_info;
 	int retval;
 	uint32_t i;
 
@@ -1350,7 +1351,7 @@ int arm_blank_check_memory(struct target *target,
 			return retval;
 	}
 
-	armv4_5_info.common_magic = ARMV4_5_COMMON_MAGIC;
+	armv4_5_info.common_magic = ARM_COMMON_MAGIC;
 	armv4_5_info.core_mode = ARM_MODE_SVC;
 	armv4_5_info.core_state = ARM_STATE_ARM;
 
@@ -1388,7 +1389,7 @@ int arm_blank_check_memory(struct target *target,
 
 static int arm_full_context(struct target *target)
 {
-	struct arm *armv4_5 = target_to_armv4_5(target);
+	struct arm *armv4_5 = target_to_arm(target);
 	unsigned num_regs = armv4_5->core_cache->num_regs;
 	struct reg *reg = armv4_5->core_cache->reg_list;
 	int retval = ERROR_OK;
@@ -1419,12 +1420,12 @@ static int arm_default_mcr(struct target *target, int cpnum,
 	return ERROR_FAIL;
 }
 
-int armv4_5_init_arch_info(struct target *target, struct arm *armv4_5)
+int arm_init_arch_info(struct target *target, struct arm *armv4_5)
 {
 	target->arch_info = armv4_5;
 	armv4_5->target = target;
 
-	armv4_5->common_magic = ARMV4_5_COMMON_MAGIC;
+	armv4_5->common_magic = ARM_COMMON_MAGIC;
 	arm_set_cpsr(armv4_5, ARM_MODE_USR);
 
 	/* core_type may be overridden by subtype logic */