X-Git-Url: https://review.openocd.org/gitweb?a=blobdiff_plain;f=src%2Ftarget%2Farmv4_5.c;h=b5e33ff5466fdf2ec010349c24e2db57830c97e0;hb=30f6142fc8570549ff42676ffe16425c6a6ef264;hp=3156c666f67a85b321dec9edc1cbc6f31567f42a;hpb=ff810723e051ed1f86cffcb565ade6b4d1fc50c8;p=openocd.git diff --git a/src/target/armv4_5.c b/src/target/armv4_5.c index 3156c666f6..b5e33ff546 100644 --- a/src/target/armv4_5.c +++ b/src/target/armv4_5.c @@ -372,6 +372,28 @@ void arm_set_cpsr(struct arm *arm, uint32_t cpsr) arm->spsr = (mode == ARMV4_5_MODE_USR || mode == ARMV4_5_MODE_SYS) ? NULL : arm->core_cache->reg_list + arm->map[16]; + + /* Older ARMs won't have the J bit */ + enum armv4_5_state state; + + if (cpsr & (1 << 5)) { /* T */ + if (cpsr & (1 << 24)) { /* J */ + LOG_WARNING("ThumbEE -- incomplete support"); + state = ARM_STATE_THUMB_EE; + } else + state = ARMV4_5_STATE_THUMB; + } else { + if (cpsr & (1 << 24)) { /* J */ + LOG_ERROR("Jazelle state handling is BROKEN!"); + state = ARMV4_5_STATE_JAZELLE; + } else + state = ARMV4_5_STATE_ARM; + } + arm->core_state = state; + + LOG_DEBUG("set CPSR %#8.8x: %s mode, %s state", (unsigned) cpsr, + arm_mode_name(mode), + armv4_5_state_strings[arm->core_state]); } /** @@ -469,7 +491,7 @@ static int armv4_5_set_core_reg(struct reg *reg, uint8_t *buf) { struct arm_reg *armv4_5 = reg->arch_info; struct target *target = armv4_5->target; - struct armv4_5_common_s *armv4_5_target = target_to_armv4_5(target); + struct arm *armv4_5_target = target_to_armv4_5(target); uint32_t value = buf_get_u32(buf, 0, 32); if (target->state != TARGET_HALTED) @@ -481,49 +503,27 @@ static int armv4_5_set_core_reg(struct reg *reg, uint8_t *buf) /* Except for CPSR, the "reg" command exposes a writeback model * for the register cache. */ - buf_set_u32(reg->value, 0, 32, value); - reg->dirty = 1; - reg->valid = 1; + if (reg == armv4_5_target->cpsr) { + arm_set_cpsr(armv4_5_target, value); - if (reg == armv4_5_target->cpsr) - { - /* FIXME handle J bit too; mostly for ThumbEE, also Jazelle */ - if (value & 0x20) - { - /* T bit should be set */ - if (armv4_5_target->core_state == ARMV4_5_STATE_ARM) - { - /* change state to Thumb */ - LOG_DEBUG("changing to Thumb state"); - armv4_5_target->core_state = ARMV4_5_STATE_THUMB; - } - } - else - { - /* T bit should be cleared */ - if (armv4_5_target->core_state == ARMV4_5_STATE_THUMB) - { - /* change state to ARM */ - LOG_DEBUG("changing to ARM state"); - armv4_5_target->core_state = ARMV4_5_STATE_ARM; - } - } - - /* REVISIT Why only update core for mode change, not also - * for state changes? Possibly older cores need to stay - * in ARM mode during halt mode debug, not execute Thumb; - * v6/v7a/v7r seem to do that automatically... + /* Older cores need help to be in ARM mode during halt + * mode debug, so we clear the J and T bits if we flush. + * For newer cores (v6/v7a/v7r) we don't need that, but + * it won't hurt since CPSR is always flushed anyway. */ - - if (armv4_5_target->core_mode != (enum armv4_5_mode)(value & 0x1f)) - { + if (armv4_5_target->core_mode != + (enum armv4_5_mode)(value & 0x1f)) { LOG_DEBUG("changing ARM core mode to '%s'", arm_mode_name(value & 0x1f)); + value &= ~((1 << 24) | (1 << 5)); armv4_5_target->write_core_reg(target, reg, 16, ARMV4_5_MODE_ANY, value); - arm_set_cpsr(armv4_5_target, value); } + } else { + buf_set_u32(reg->value, 0, 32, value); + reg->valid = 1; } + reg->dirty = 1; return ERROR_OK; } @@ -583,7 +583,7 @@ struct reg_cache* armv4_5_build_reg_cache(struct target *target, struct arm *arm int armv4_5_arch_state(struct target *target) { - struct armv4_5_common_s *armv4_5 = target_to_armv4_5(target); + struct arm *armv4_5 = target_to_armv4_5(target); if (armv4_5->common_magic != ARMV4_5_COMMON_MAGIC) { @@ -607,7 +607,7 @@ int armv4_5_arch_state(struct target *target) COMMAND_HANDLER(handle_armv4_5_reg_command) { struct target *target = get_current_target(CMD_CTX); - struct armv4_5_common_s *armv4_5 = target_to_armv4_5(target); + struct arm *armv4_5 = target_to_armv4_5(target); unsigned num_regs; struct reg *regs; @@ -694,7 +694,7 @@ COMMAND_HANDLER(handle_armv4_5_reg_command) COMMAND_HANDLER(handle_armv4_5_core_state_command) { struct target *target = get_current_target(CMD_CTX); - struct armv4_5_common_s *armv4_5 = target_to_armv4_5(target); + struct arm *armv4_5 = target_to_armv4_5(target); if (!is_arm(armv4_5)) { @@ -790,31 +790,42 @@ usage: return retval; } -int armv4_5_register_commands(struct command_context *cmd_ctx) -{ - struct command *armv4_5_cmd; - - armv4_5_cmd = register_command(cmd_ctx, NULL, "arm", - NULL, COMMAND_ANY, - "generic ARM commands"); - - register_command(cmd_ctx, armv4_5_cmd, "reg", - handle_armv4_5_reg_command, COMMAND_EXEC, - "display ARM core registers"); - register_command(cmd_ctx, armv4_5_cmd, "core_state", - handle_armv4_5_core_state_command, COMMAND_EXEC, - "display/change ARM core state "); - register_command(cmd_ctx, armv4_5_cmd, "disassemble", - handle_armv4_5_disassemble_command, COMMAND_EXEC, - "disassemble instructions " - "
[ ['thumb']]"); - - return ERROR_OK; -} +static const struct command_registration arm_exec_command_handlers[] = { + { + .name = "reg", + .handler = &handle_armv4_5_reg_command, + .mode = COMMAND_EXEC, + .help = "display ARM core registers", + }, + { + .name = "core_state", + .handler = &handle_armv4_5_core_state_command, + .mode = COMMAND_EXEC, + .usage = "", + .help = "display/change ARM core state", + }, + { + .name = "disassemble", + .handler = &handle_armv4_5_disassemble_command, + .mode = COMMAND_EXEC, + .usage = "
[ ['thumb']]", + .help = "disassemble instructions ", + }, + COMMAND_REGISTRATION_DONE +}; +const struct command_registration arm_command_handlers[] = { + { + .name = "arm", + .mode = COMMAND_ANY, + .help = "ARM command group", + .chain = arm_exec_command_handlers, + }, + COMMAND_REGISTRATION_DONE +}; int armv4_5_get_gdb_reg_list(struct target *target, struct reg **reg_list[], int *reg_list_size) { - struct armv4_5_common_s *armv4_5 = target_to_armv4_5(target); + struct arm *armv4_5 = target_to_armv4_5(target); int i; if (!is_arm_mode(armv4_5->core_mode)) @@ -839,7 +850,7 @@ int armv4_5_get_gdb_reg_list(struct target *target, struct reg **reg_list[], int static int armv4_5_run_algorithm_completion(struct target *target, uint32_t exit_point, int timeout_ms, void *arch_info) { int retval; - struct armv4_5_common_s *armv4_5 = target_to_armv4_5(target); + struct arm *armv4_5 = target_to_armv4_5(target); if ((retval = target_wait_state(target, TARGET_HALTED, timeout_ms)) != ERROR_OK) { @@ -868,9 +879,15 @@ static int armv4_5_run_algorithm_completion(struct target *target, uint32_t exit return ERROR_OK; } -int armv4_5_run_algorithm_inner(struct target *target, int num_mem_params, struct mem_param *mem_params, int num_reg_params, struct reg_param *reg_params, uint32_t entry_point, uint32_t exit_point, int timeout_ms, void *arch_info, int (*run_it)(struct target *target, uint32_t exit_point, int timeout_ms, void *arch_info)) +int armv4_5_run_algorithm_inner(struct target *target, + int num_mem_params, struct mem_param *mem_params, + int num_reg_params, struct reg_param *reg_params, + uint32_t entry_point, uint32_t exit_point, + int timeout_ms, void *arch_info, + int (*run_it)(struct target *target, uint32_t exit_point, + int timeout_ms, void *arch_info)) { - struct armv4_5_common_s *armv4_5 = target_to_armv4_5(target); + struct arm *armv4_5 = target_to_armv4_5(target); struct armv4_5_algorithm *armv4_5_algorithm_info = arch_info; enum armv4_5_state core_state = armv4_5->core_state; uint32_t context[17]; @@ -878,6 +895,7 @@ int armv4_5_run_algorithm_inner(struct target *target, int num_mem_params, struc int exit_breakpoint_size = 0; int i; int retval = ERROR_OK; + LOG_DEBUG("Running algorithm"); if (armv4_5_algorithm_info->common_magic != ARMV4_5_COMMON_MAGIC) @@ -1221,7 +1239,7 @@ int arm_blank_check_memory(struct target *target, static int arm_full_context(struct target *target) { - struct armv4_5_common_s *armv4_5 = target_to_armv4_5(target); + struct arm *armv4_5 = target_to_armv4_5(target); unsigned num_regs = armv4_5->core_cache->num_regs; struct reg *reg = armv4_5->core_cache->reg_list; int retval = ERROR_OK; @@ -1237,10 +1255,10 @@ static int arm_full_context(struct target *target) int armv4_5_init_arch_info(struct target *target, struct arm *armv4_5) { target->arch_info = armv4_5; + armv4_5->target = target; armv4_5->common_magic = ARMV4_5_COMMON_MAGIC; arm_set_cpsr(armv4_5, ARMV4_5_MODE_USR); - armv4_5->core_state = ARMV4_5_STATE_ARM; /* core_type may be overridden by subtype logic */ armv4_5->core_type = ARMV4_5_MODE_ANY;