X-Git-Url: https://review.openocd.org/gitweb?a=blobdiff_plain;f=src%2Ftarget%2Farmv4_5.c;h=a2f055753bfa1d176af1e90209dd9f3af9a27ac7;hb=1e6970dafdccfec388d1a816c2019f9c6b26e338;hp=633e1c717ff757f46acf545fe0a645260752dda3;hpb=e1e1d4742c4f75603e177a3dc4338a7e265bbabb;p=openocd.git

diff --git a/src/target/armv4_5.c b/src/target/armv4_5.c
index 633e1c717f..a2f055753b 100644
--- a/src/target/armv4_5.c
+++ b/src/target/armv4_5.c
@@ -21,7 +21,7 @@
  *   You should have received a copy of the GNU General Public License     *
  *   along with this program; if not, write to the                         *
  *   Free Software Foundation, Inc.,                                       *
- *   59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.             *
+ *   51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.           *
  ***************************************************************************/
 
 #ifdef HAVE_CONFIG_H
@@ -140,6 +140,21 @@ static const struct {
 		.n_indices = ARRAY_SIZE(arm_mon_indices),
 		.indices = arm_mon_indices,
 	},
+
+	/* These special modes are currently only supported
+	 * by ARMv6M and ARMv7M profiles */
+	{
+		.name = "Thread",
+		.psr = ARM_MODE_THREAD,
+	},
+	{
+		.name = "Thread (User)",
+		.psr = ARM_MODE_USER_THREAD,
+	},
+	{
+		.name = "Handler",
+		.psr = ARM_MODE_HANDLER,
+	},
 };
 
 /** Map PSR mode bits to the name of an ARM processor operating mode. */
@@ -414,7 +429,11 @@ struct reg *arm_reg_current(struct arm *arm, unsigned regnum)
 	if (regnum > 16)
 		return NULL;
 
-	r = arm->core_cache->reg_list + arm->map[regnum];
+	if (!arm->map) {
+		LOG_ERROR("Register map is not available yet, the target is not fully initialised");
+		r = arm->core_cache->reg_list + regnum;
+	} else
+		r = arm->core_cache->reg_list + arm->map[regnum];
 
 	/* e.g. invalid CPSR said "secure monitor" mode on a core
 	 * that doesn't support it...
@@ -1002,13 +1021,13 @@ static const struct command_registration arm_exec_command_handlers[] = {
 		.mode = COMMAND_EXEC,
 		.jim_handler = &jim_mcrmrc,
 		.help = "write coprocessor register",
-		.usage = "cpnum op1 CRn op2 CRm value",
+		.usage = "cpnum op1 CRn CRm op2 value",
 	},
 	{
 		.name = "mrc",
 		.jim_handler = &jim_mcrmrc,
 		.help = "read coprocessor register",
-		.usage = "cpnum op1 CRn op2 CRm",
+		.usage = "cpnum op1 CRn CRm op2",
 	},
 	{
 		"semihosting",
@@ -1032,7 +1051,8 @@ const struct command_registration arm_command_handlers[] = {
 };
 
 int arm_get_gdb_reg_list(struct target *target,
-	struct reg **reg_list[], int *reg_list_size)
+	struct reg **reg_list[], int *reg_list_size,
+	enum target_register_class reg_class)
 {
 	struct arm *arm = target_to_arm(target);
 	int i;
@@ -1300,7 +1320,7 @@ int arm_checksum_memory(struct target *target,
 	uint32_t address, uint32_t count, uint32_t *checksum)
 {
 	struct working_area *crc_algorithm;
-	struct arm_algorithm armv4_5_info;
+	struct arm_algorithm arm_algo;
 	struct arm *arm = target_to_arm(target);
 	struct reg_param reg_params[2];
 	int retval;
@@ -1352,9 +1372,9 @@ int arm_checksum_memory(struct target *target,
 			return retval;
 	}
 
-	armv4_5_info.common_magic = ARM_COMMON_MAGIC;
-	armv4_5_info.core_mode = ARM_MODE_SVC;
-	armv4_5_info.core_state = ARM_STATE_ARM;
+	arm_algo.common_magic = ARM_COMMON_MAGIC;
+	arm_algo.core_mode = ARM_MODE_SVC;
+	arm_algo.core_state = ARM_STATE_ARM;
 
 	init_reg_param(&reg_params[0], "r0", 32, PARAM_IN_OUT);
 	init_reg_param(&reg_params[1], "r1", 32, PARAM_OUT);
@@ -1372,7 +1392,7 @@ int arm_checksum_memory(struct target *target,
 	retval = target_run_algorithm(target, 0, NULL, 2, reg_params,
 			crc_algorithm->address,
 			exit_var,
-			timeout, &armv4_5_info);
+			timeout, &arm_algo);
 	if (retval != ERROR_OK) {
 		LOG_ERROR("error executing ARM crc algorithm");
 		destroy_reg_param(&reg_params[0]);
@@ -1402,7 +1422,7 @@ int arm_blank_check_memory(struct target *target,
 {
 	struct working_area *check_algorithm;
 	struct reg_param reg_params[3];
-	struct arm_algorithm armv4_5_info;
+	struct arm_algorithm arm_algo;
 	struct arm *arm = target_to_arm(target);
 	int retval;
 	uint32_t i;
@@ -1436,9 +1456,9 @@ int arm_blank_check_memory(struct target *target,
 			return retval;
 	}
 
-	armv4_5_info.common_magic = ARM_COMMON_MAGIC;
-	armv4_5_info.core_mode = ARM_MODE_SVC;
-	armv4_5_info.core_state = ARM_STATE_ARM;
+	arm_algo.common_magic = ARM_COMMON_MAGIC;
+	arm_algo.core_mode = ARM_MODE_SVC;
+	arm_algo.core_state = ARM_STATE_ARM;
 
 	init_reg_param(&reg_params[0], "r0", 32, PARAM_OUT);
 	buf_set_u32(reg_params[0].value, 0, 32, address);
@@ -1456,7 +1476,7 @@ int arm_blank_check_memory(struct target *target,
 	retval = target_run_algorithm(target, 0, NULL, 3, reg_params,
 			check_algorithm->address,
 			exit_var,
-			10000, &armv4_5_info);
+			10000, &arm_algo);
 	if (retval != ERROR_OK) {
 		destroy_reg_param(&reg_params[0]);
 		destroy_reg_param(&reg_params[1]);