X-Git-Url: https://review.openocd.org/gitweb?a=blobdiff_plain;f=src%2Ftarget%2Farmv4_5.c;h=02a731cac423e4ad627abae066eb822ce24341e6;hb=3c58540e0283a452a7606ba22e693df10d746d54;hp=00fb2f07856fe0c3d300990a87ceecde212e09a3;hpb=a582e9a8d183c56d1aa8ae18afc1c11e2cbd6d2d;p=openocd.git

diff --git a/src/target/armv4_5.c b/src/target/armv4_5.c
index 00fb2f0785..02a731cac4 100644
--- a/src/target/armv4_5.c
+++ b/src/target/armv4_5.c
@@ -174,14 +174,14 @@ int armv4_5_mode_to_number(enum armv4_5_mode mode)
 {
 	switch (mode)
 	{
-		case 16: return 0; break;
-		case 17: return 1; break;
-		case 18: return 2; break;
-		case 19: return 3; break;
-		case 23: return 4; break;
-		case 27: return 5; break;
-		case 31: return 6; break;
-		case -1: return 0; break;	/* map MODE_ANY to user mode */
+		case ARMV4_5_MODE_USR: return 0; break;
+		case ARMV4_5_MODE_FIQ: return 1; break;
+		case ARMV4_5_MODE_IRQ: return 2; break;
+		case ARMV4_5_MODE_SVC: return 3; break;
+		case ARMV4_5_MODE_ABT: return 4; break;
+		case ARMV4_5_MODE_UND: return 5; break;
+		case ARMV4_5_MODE_SYS: return 6; break;
+		case ARMV4_5_MODE_ANY: return 0; break;	/* map MODE_ANY to user mode */
 		default: 
 			ERROR("invalid mode value encountered");
 			return -1;
@@ -257,6 +257,13 @@ int armv4_5_set_core_reg(reg_t *reg, u8 *buf)
 				armv4_5_target->core_state = ARMV4_5_STATE_ARM;	
 			}
 		}
+		
+		if (armv4_5_target->core_mode != (value & 0x1f))
+		{
+			DEBUG("changing ARM core mode to '%s'", armv4_5_mode_strings[armv4_5_mode_to_number(value & 0x1f)]);
+			armv4_5_target->core_mode = value & 0x1f;
+			armv4_5_target->write_core_reg(target, 16, ARMV4_5_MODE_ANY, value);
+		}
 	}
 	
 	buf_set_u32(reg->value, 0, 32, value);
@@ -285,7 +292,7 @@ reg_cache_t* armv4_5_build_reg_cache(target_t *target, armv4_5_common_t *armv4_5
 	int num_regs = 37;
 	reg_cache_t *cache = malloc(sizeof(reg_cache_t));
 	reg_t *reg_list = malloc(sizeof(reg_t) * num_regs);
-	armv4_5_core_reg_t *arch_info = malloc(sizeof(reg_t) * num_regs);
+	armv4_5_core_reg_t *arch_info = malloc(sizeof(armv4_5_core_reg_t) * num_regs);
 	int i;
 	
 	cache->name = "arm v4/5 registers";
@@ -442,7 +449,7 @@ int handle_armv4_5_disassemble_command(struct command_context_s *cmd_ctx, char *
 	for (i = 0; i < count; i++)
 	{
 		target_read_u32(target, address, &opcode);
-		evaluate_opcode(opcode, address, &cur_instruction);
+		arm_evaluate_opcode(opcode, address, &cur_instruction);
 		command_print(cmd_ctx, "%s", cur_instruction.text);
 		address += (thumb) ? 2 : 4;
 	}
@@ -598,6 +605,13 @@ int armv4_5_run_algorithm(struct target_s *target, int num_mem_params, mem_param
 		}
 	}
 	
+	if ((retval != ERROR_TARGET_TIMEOUT) && 
+		(buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32) != exit_point))
+	{
+		WARNING("target reentered debug state, but not at the desired exit point: 0x%4.4x",
+			buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32)); 
+	}
+	
 	breakpoint_remove(target, exit_point);
 	
 	for (i = 0; i < num_mem_params; i++)
@@ -630,7 +644,7 @@ int armv4_5_run_algorithm(struct target_s *target, int num_mem_params, mem_param
 	
 	for (i = 0; i <= 16; i++)
 	{
-		DEBUG("restoring register %s with value 0x%8.8x", ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_algorithm_info->core_mode, i).name, buf_get_u32(ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_algorithm_info->core_mode, i).value, 0, 32));
+		DEBUG("restoring register %s with value 0x%8.8x", ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_algorithm_info->core_mode, i).name, context[i]);
 		buf_set_u32(ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_algorithm_info->core_mode, i).value, 0, 32, context[i]);
 		ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_algorithm_info->core_mode, i).valid = 1;
 		ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_algorithm_info->core_mode, i).dirty = 1;