X-Git-Url: https://review.openocd.org/gitweb?a=blobdiff_plain;f=src%2Ftarget%2Farm_simulator.c;h=cb1f65180aa4ecedfd2653d8b42b38170df75d3c;hb=56e01714203406b50b40dd7738983e3b019d4df2;hp=46cd5587311fb116dc43db806d5f5cafefe7fe27;hpb=0f1163e823c6ca3c2a81fa296157f5dde0635fea;p=openocd.git diff --git a/src/target/arm_simulator.c b/src/target/arm_simulator.c index 46cd558731..cb1f65180a 100644 --- a/src/target/arm_simulator.c +++ b/src/target/arm_simulator.c @@ -27,8 +27,9 @@ #include "armv4_5.h" #include "arm_disassembler.h" #include "arm_simulator.h" -#include "log.h" -#include "binarybuffer.h" +#include +#include "register.h" +#include static uint32_t arm_shift(uint8_t shift, uint32_t Rm, @@ -134,7 +135,7 @@ static uint32_t arm_shifter_operand(struct arm_sim_interface *sim, uint32_t return_value; int instruction_size; - if (sim->get_state(sim) == ARMV4_5_STATE_ARM) + if (sim->get_state(sim) == ARM_STATE_ARM) instruction_size = 4; else instruction_size = 2; @@ -285,7 +286,7 @@ int arm_simulate_step_core(struct target *target, int instruction_size; int retval = ERROR_OK; - if (sim->get_state(sim) == ARMV4_5_STATE_ARM) + if (sim->get_state(sim) == ARM_STATE_ARM) { uint32_t opcode; @@ -391,7 +392,7 @@ int arm_simulate_step_core(struct target *target, else if (instruction.type == ARM_BL) { uint32_t old_pc = sim->get_reg(sim, 15); - int T = (sim->get_state(sim) == ARMV4_5_STATE_THUMB); + int T = (sim->get_state(sim) == ARM_STATE_THUMB); sim->set_reg_mode(sim, 14, old_pc + 4 + T); sim->set_reg(sim, 15, target); } @@ -399,27 +400,27 @@ int arm_simulate_step_core(struct target *target, { if (target & 0x1) { - sim->set_state(sim, ARMV4_5_STATE_THUMB); + sim->set_state(sim, ARM_STATE_THUMB); } else { - sim->set_state(sim, ARMV4_5_STATE_ARM); + sim->set_state(sim, ARM_STATE_ARM); } sim->set_reg(sim, 15, target & 0xfffffffe); } else if (instruction.type == ARM_BLX) { uint32_t old_pc = sim->get_reg(sim, 15); - int T = (sim->get_state(sim) == ARMV4_5_STATE_THUMB); + int T = (sim->get_state(sim) == ARM_STATE_THUMB); sim->set_reg_mode(sim, 14, old_pc + 4 + T); if (target & 0x1) { - sim->set_state(sim, ARMV4_5_STATE_THUMB); + sim->set_state(sim, ARM_STATE_THUMB); } else { - sim->set_state(sim, ARMV4_5_STATE_ARM); + sim->set_state(sim, ARM_STATE_ARM); } sim->set_reg(sim, 15, target & 0xfffffffe); } @@ -492,9 +493,9 @@ int arm_simulate_step_core(struct target *target, if (instruction.info.data_proc.Rd == 15) { sim->set_reg_mode(sim, 15, Rd & ~1); if (Rd & 1) - sim->set_state(sim, ARMV4_5_STATE_THUMB); + sim->set_state(sim, ARM_STATE_THUMB); else - sim->set_state(sim, ARMV4_5_STATE_ARM); + sim->set_state(sim, ARM_STATE_ARM); return ERROR_OK; } sim->set_reg_mode(sim, instruction.info.data_proc.Rd, Rd); @@ -604,9 +605,9 @@ int arm_simulate_step_core(struct target *target, if (instruction.info.load_store.Rd == 15) { sim->set_reg_mode(sim, 15, load_value & ~1); if (load_value & 1) - sim->set_state(sim, ARMV4_5_STATE_THUMB); + sim->set_state(sim, ARM_STATE_THUMB); else - sim->set_state(sim, ARMV4_5_STATE_ARM); + sim->set_state(sim, ARM_STATE_ARM); return ERROR_OK; } sim->set_reg_mode(sim, instruction.info.load_store.Rd, load_value); @@ -664,7 +665,7 @@ int arm_simulate_step_core(struct target *target, } else { - enum armv4_5_mode mode = sim->get_mode(sim); + enum arm_mode mode = sim->get_mode(sim); int update_cpsr = 0; if (instruction.info.load_store_multiple.S) @@ -672,7 +673,7 @@ int arm_simulate_step_core(struct target *target, if (instruction.info.load_store_multiple.register_list & 0x8000) update_cpsr = 1; else - mode = ARMV4_5_MODE_USR; + mode = ARM_MODE_USR; } for (i = 0; i < 16; i++) @@ -683,9 +684,9 @@ int arm_simulate_step_core(struct target *target, uint32_t val = load_values[i]; sim->set_reg_mode(sim, i, val & ~1); if (val & 1) - sim->set_state(sim, ARMV4_5_STATE_THUMB); + sim->set_state(sim, ARM_STATE_THUMB); else - sim->set_state(sim, ARMV4_5_STATE_ARM); + sim->set_state(sim, ARM_STATE_ARM); } else { sim->set_reg_mode(sim, i, load_values[i]); } @@ -720,7 +721,7 @@ int arm_simulate_step_core(struct target *target, uint32_t Rn = sim->get_reg_mode(sim, instruction.info.load_store_multiple.Rn); int bits_set = 0; - enum armv4_5_mode mode = sim->get_mode(sim); + enum arm_mode mode = sim->get_mode(sim); for (i = 0; i < 16; i++) { @@ -730,7 +731,7 @@ int arm_simulate_step_core(struct target *target, if (instruction.info.load_store_multiple.S) { - mode = ARMV4_5_MODE_USR; + mode = ARM_MODE_USR; } switch (instruction.info.load_store_multiple.addressing_mode) @@ -820,17 +821,17 @@ static uint32_t armv4_5_get_cpsr(struct arm_sim_interface *sim, int pos, int bit { struct arm *armv4_5 = (struct arm *)sim->user_data; - return buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, pos, bits); + return buf_get_u32(armv4_5->cpsr->value, pos, bits); } -static enum armv4_5_state armv4_5_get_state(struct arm_sim_interface *sim) +static enum arm_state armv4_5_get_state(struct arm_sim_interface *sim) { struct arm *armv4_5 = (struct arm *)sim->user_data; return armv4_5->core_state; } -static void armv4_5_set_state(struct arm_sim_interface *sim, enum armv4_5_state mode) +static void armv4_5_set_state(struct arm_sim_interface *sim, enum arm_state mode) { struct arm *armv4_5 = (struct arm *)sim->user_data; @@ -838,7 +839,7 @@ static void armv4_5_set_state(struct arm_sim_interface *sim, enum armv4_5_state } -static enum armv4_5_mode armv4_5_get_mode(struct arm_sim_interface *sim) +static enum arm_mode armv4_5_get_mode(struct arm_sim_interface *sim) { struct arm *armv4_5 = (struct arm *)sim->user_data; @@ -849,7 +850,7 @@ static enum armv4_5_mode armv4_5_get_mode(struct arm_sim_interface *sim) int arm_simulate_step(struct target *target, uint32_t *dry_run_pc) { - struct armv4_5_common_s *armv4_5 = target_to_armv4_5(target); + struct arm *armv4_5 = target_to_armv4_5(target); struct arm_sim_interface sim; sim.user_data = armv4_5;