X-Git-Url: https://review.openocd.org/gitweb?a=blobdiff_plain;f=src%2Ftarget%2Farm_simulator.c;h=c50a52cd9cfa8ceb456bf0cd7da1dfef81a6c2e3;hb=68937cadfb42026b4c8b2c9e43acaf3fb409c4db;hp=e2f49c390331dbc988178d9159e7850c702b0e9a;hpb=6726b78707f349d389c30ce85713047eb761b7ca;p=openocd.git

diff --git a/src/target/arm_simulator.c b/src/target/arm_simulator.c
index e2f49c3903..c50a52cd9c 100644
--- a/src/target/arm_simulator.c
+++ b/src/target/arm_simulator.c
@@ -309,19 +309,17 @@ int arm_simulate_step_core(target_t *target, uint32_t *dry_run_pc, struct arm_si
 	{
 		uint16_t opcode;
 
-		if ((retval = target_read_u16(target, current_pc, &opcode)) != ERROR_OK)
-		{
+		retval = target_read_u16(target, current_pc, &opcode);
+		if (retval != ERROR_OK)
 			return retval;
-		}
-		if ((retval = thumb_evaluate_opcode(opcode, current_pc, &instruction)) != ERROR_OK)
-		{
+		retval = thumb_evaluate_opcode(opcode, current_pc, &instruction);
+		 if (retval != ERROR_OK)
 			return retval;
-			}
 		instruction_size = 2;
 
 		/* check condition code (only for branch instructions) */
-		if ((!thumb_pass_branch_condition(sim->get_cpsr(sim, 0, 32), opcode)) &&
-			(instruction.type == ARM_B))
+		if (instruction.type == ARM_B &&
+		    !thumb_pass_branch_condition(sim->get_cpsr(sim, 0, 32), opcode))
 		{
 			if (dry_run_pc)
 			{
@@ -334,6 +332,18 @@ int arm_simulate_step_core(target_t *target, uint32_t *dry_run_pc, struct arm_si
 
 			return ERROR_OK;
 		}
+
+		/* Deal with 32-bit BL/BLX */
+		if ((opcode & 0xf800) == 0xf000) {
+			uint32_t high = instruction.info.b_bl_bx_blx.target_address;
+			retval = target_read_u16(target, current_pc+2, &opcode);
+			if (retval != ERROR_OK)
+				return retval;
+			retval = thumb_evaluate_opcode(opcode, current_pc, &instruction);
+			if (retval != ERROR_OK)
+				return retval;
+			instruction.info.b_bl_bx_blx.target_address += high;
+		}
 	}
 
 	/* examine instruction type */
@@ -370,7 +380,8 @@ int arm_simulate_step_core(target_t *target, uint32_t *dry_run_pc, struct arm_si
 			else if (instruction.type == ARM_BL)
 			{
 				uint32_t old_pc = sim->get_reg(sim, 15);
-				sim->set_reg_mode(sim, 14, old_pc + 4);
+				int T = (sim->get_state(sim) == ARMV4_5_STATE_THUMB);
+				sim->set_reg_mode(sim, 14, old_pc + 4 + T);
 				sim->set_reg(sim, 15, target);
 			}
 			else if (instruction.type == ARM_BX)
@@ -388,7 +399,8 @@ int arm_simulate_step_core(target_t *target, uint32_t *dry_run_pc, struct arm_si
 			else if (instruction.type == ARM_BLX)
 			{
 				uint32_t old_pc = sim->get_reg(sim, 15);
-				sim->set_reg_mode(sim, 14, old_pc + 4);
+				int T = (sim->get_state(sim) == ARMV4_5_STATE_THUMB);
+				sim->set_reg_mode(sim, 14, old_pc + 4 + T);
 
 				if (target & 0x1)
 				{
@@ -455,24 +467,24 @@ int arm_simulate_step_core(target_t *target, uint32_t *dry_run_pc, struct arm_si
 		if (dry_run_pc)
 		{
 			if (instruction.info.data_proc.Rd == 15)
-			{
-				*dry_run_pc = Rd;
-				return ERROR_OK;
-			}
+				*dry_run_pc = Rd & ~1;
 			else
-			{
 				*dry_run_pc = current_pc + instruction_size;
-			}
 
 			return ERROR_OK;
 		}
 		else
 		{
+			if (instruction.info.data_proc.Rd == 15) {
+				sim->set_reg_mode(sim, 15, Rd & ~1);
+				if (Rd & 1)
+					sim->set_state(sim, ARMV4_5_STATE_THUMB);
+				else
+					sim->set_state(sim, ARMV4_5_STATE_ARM);
+				return ERROR_OK;
+			}
 			sim->set_reg_mode(sim, instruction.info.data_proc.Rd, Rd);
 			LOG_WARNING("no updating of flags yet");
-
-			if (instruction.info.data_proc.Rd == 15)
-				return ERROR_OK;
 		}
 	}
 	/* compare instructions (CMP, CMN, TST, TEQ) */
@@ -556,15 +568,9 @@ int arm_simulate_step_core(target_t *target, uint32_t *dry_run_pc, struct arm_si
 		if (dry_run_pc)
 		{
 			if (instruction.info.load_store.Rd == 15)
-			{
-				*dry_run_pc = load_value;
-				return ERROR_OK;
-			}
+				*dry_run_pc = load_value & ~1;
 			else
-			{
 				*dry_run_pc = current_pc + instruction_size;
-			}
-
 			return ERROR_OK;
 		}
 		else
@@ -574,10 +580,16 @@ int arm_simulate_step_core(target_t *target, uint32_t *dry_run_pc, struct arm_si
 			{
 				sim->set_reg_mode(sim, instruction.info.load_store.Rn, modified_address);
 			}
-			sim->set_reg_mode(sim, instruction.info.load_store.Rd, load_value);
 
-			if (instruction.info.load_store.Rd == 15)
+			if (instruction.info.load_store.Rd == 15) {
+				sim->set_reg_mode(sim, 15, load_value & ~1);
+				if (load_value & 1)
+					sim->set_state(sim, ARMV4_5_STATE_THUMB);
+				else
+					sim->set_state(sim, ARMV4_5_STATE_ARM);
 				return ERROR_OK;
+			}
+			sim->set_reg_mode(sim, instruction.info.load_store.Rd, load_value);
 		}
 	}
 	/* load multiple instruction */
@@ -626,7 +638,7 @@ int arm_simulate_step_core(target_t *target, uint32_t *dry_run_pc, struct arm_si
 		{
 			if (instruction.info.load_store_multiple.register_list & 0x8000)
 			{
-				*dry_run_pc = load_values[15];
+				*dry_run_pc = load_values[15] & ~1;
 				return ERROR_OK;
 			}
 		}
@@ -647,7 +659,16 @@ int arm_simulate_step_core(target_t *target, uint32_t *dry_run_pc, struct arm_si
 			{
 				if (instruction.info.load_store_multiple.register_list & (1 << i))
 				{
-					sim->set_reg_mode(sim, i, load_values[i]);
+					if (i == 15) {
+						uint32_t val = load_values[i];
+					sim->set_reg_mode(sim, i, val & ~1);
+					if (val & 1)
+						sim->set_state(sim, ARMV4_5_STATE_THUMB);
+					else
+						sim->set_state(sim, ARMV4_5_STATE_ARM);
+					} else {
+						sim->set_reg_mode(sim, i, load_values[i]);
+					}
 				}
 			}