X-Git-Url: https://review.openocd.org/gitweb?a=blobdiff_plain;f=src%2Ftarget%2Farm_simulator.c;h=0a34cfcf4967fd207e6a2a84673b85aa7b9e1af4;hb=c8b57198025c414f8d19577e6846021843c2a751;hp=a1ed54c7fc1c7d1b5367d16b4e8931453d809c02;hpb=31e3ea7c19d39589ac9a8b2220331206b6d1e25c;p=openocd.git

diff --git a/src/target/arm_simulator.c b/src/target/arm_simulator.c
index a1ed54c7fc..0a34cfcf49 100644
--- a/src/target/arm_simulator.c
+++ b/src/target/arm_simulator.c
@@ -24,6 +24,7 @@
 #include "config.h"
 #endif
 
+#include "arm.h"
 #include "armv4_5.h"
 #include "arm_disassembler.h"
 #include "arm_simulator.h"
@@ -278,7 +279,7 @@ static int thumb_pass_branch_condition(uint32_t cpsr, uint16_t opcode)
  * if the dry_run_pc argument is provided, no state is changed,
  * but the new pc is stored in the variable pointed at by the argument
  */
-int arm_simulate_step_core(struct target *target,
+static int arm_simulate_step_core(struct target *target,
 		uint32_t *dry_run_pc, struct arm_sim_interface *sim)
 {
 	uint32_t current_pc = sim->get_reg(sim, 15);
@@ -363,42 +364,42 @@ int arm_simulate_step_core(struct target *target,
 	/* branch instructions */
 	if ((instruction.type >= ARM_B) && (instruction.type <= ARM_BLX))
 	{
-		uint32_t target;
+		uint32_t target_address;
 
 		if (instruction.info.b_bl_bx_blx.reg_operand == -1)
 		{
-			target = instruction.info.b_bl_bx_blx.target_address;
+			target_address = instruction.info.b_bl_bx_blx.target_address;
 		}
 		else
 		{
-			target = sim->get_reg_mode(sim, instruction.info.b_bl_bx_blx.reg_operand);
+			target_address = sim->get_reg_mode(sim, instruction.info.b_bl_bx_blx.reg_operand);
 			if (instruction.info.b_bl_bx_blx.reg_operand == 15)
 			{
-				target += 2 * instruction_size;
+				target_address += 2 * instruction_size;
 			}
 		}
 
 		if (dry_run_pc)
 		{
-			*dry_run_pc = target & ~1;
+			*dry_run_pc = target_address & ~1;
 			return ERROR_OK;
 		}
 		else
 		{
 			if (instruction.type == ARM_B)
 			{
-				sim->set_reg(sim, 15, target);
+				sim->set_reg(sim, 15, target_address);
 			}
 			else if (instruction.type == ARM_BL)
 			{
 				uint32_t old_pc = sim->get_reg(sim, 15);
 				int T = (sim->get_state(sim) == ARM_STATE_THUMB);
 				sim->set_reg_mode(sim, 14, old_pc + 4 + T);
-				sim->set_reg(sim, 15, target);
+				sim->set_reg(sim, 15, target_address);
 			}
 			else if (instruction.type == ARM_BX)
 			{
-				if (target & 0x1)
+				if (target_address & 0x1)
 				{
 					sim->set_state(sim, ARM_STATE_THUMB);
 				}
@@ -406,7 +407,7 @@ int arm_simulate_step_core(struct target *target,
 				{
 					sim->set_state(sim, ARM_STATE_ARM);
 				}
-				sim->set_reg(sim, 15, target & 0xfffffffe);
+				sim->set_reg(sim, 15, target_address & 0xfffffffe);
 			}
 			else if (instruction.type == ARM_BLX)
 			{
@@ -414,7 +415,7 @@ int arm_simulate_step_core(struct target *target,
 				int T = (sim->get_state(sim) == ARM_STATE_THUMB);
 				sim->set_reg_mode(sim, 14, old_pc + 4 + T);
 
-				if (target & 0x1)
+				if (target_address & 0x1)
 				{
 					sim->set_state(sim, ARM_STATE_THUMB);
 				}
@@ -422,7 +423,7 @@ int arm_simulate_step_core(struct target *target,
 				{
 					sim->set_state(sim, ARM_STATE_ARM);
 				}
-				sim->set_reg(sim, 15, target & 0xfffffffe);
+				sim->set_reg(sim, 15, target_address & 0xfffffffe);
 			}
 
 			return ERROR_OK;
@@ -665,15 +666,12 @@ int arm_simulate_step_core(struct target *target,
 		}
 		else
 		{
-			enum armv4_5_mode mode = sim->get_mode(sim);
 			int update_cpsr = 0;
 
 			if (instruction.info.load_store_multiple.S)
 			{
 				if (instruction.info.load_store_multiple.register_list & 0x8000)
 					update_cpsr = 1;
-				else
-					mode = ARMV4_5_MODE_USR;
 			}
 
 			for (i = 0; i < 16; i++)
@@ -721,7 +719,6 @@ int arm_simulate_step_core(struct target *target,
 			uint32_t Rn = sim->get_reg_mode(sim,
 					instruction.info.load_store_multiple.Rn);
 			int bits_set = 0;
-			enum armv4_5_mode mode = sim->get_mode(sim);
 
 			for (i = 0; i < 16; i++)
 			{
@@ -729,11 +726,6 @@ int arm_simulate_step_core(struct target *target,
 					bits_set++;
 			}
 
-			if (instruction.info.load_store_multiple.S)
-			{
-				mode = ARMV4_5_MODE_USR;
-			}
-
 			switch (instruction.info.load_store_multiple.addressing_mode)
 			{
 				case 0: /* Increment after */
@@ -824,14 +816,14 @@ static uint32_t armv4_5_get_cpsr(struct arm_sim_interface *sim, int pos, int bit
 	return buf_get_u32(armv4_5->cpsr->value, pos, bits);
 }
 
-static enum armv4_5_state armv4_5_get_state(struct arm_sim_interface *sim)
+static enum arm_state armv4_5_get_state(struct arm_sim_interface *sim)
 {
 	struct arm *armv4_5 = (struct arm *)sim->user_data;
 
 	return armv4_5->core_state;
 }
 
-static void armv4_5_set_state(struct arm_sim_interface *sim, enum armv4_5_state mode)
+static void armv4_5_set_state(struct arm_sim_interface *sim, enum arm_state mode)
 {
 	struct arm *armv4_5 = (struct arm *)sim->user_data;
 
@@ -839,7 +831,7 @@ static void armv4_5_set_state(struct arm_sim_interface *sim, enum armv4_5_state
 }
 
 
-static enum armv4_5_mode armv4_5_get_mode(struct arm_sim_interface *sim)
+static enum arm_mode armv4_5_get_mode(struct arm_sim_interface *sim)
 {
 	struct arm *armv4_5 = (struct arm *)sim->user_data;
 
@@ -850,7 +842,7 @@ static enum armv4_5_mode armv4_5_get_mode(struct arm_sim_interface *sim)
 
 int arm_simulate_step(struct target *target, uint32_t *dry_run_pc)
 {
-	struct arm *armv4_5 = target_to_armv4_5(target);
+	struct arm *armv4_5 = target_to_arm(target);
 	struct arm_sim_interface sim;
 
 	sim.user_data = armv4_5;