X-Git-Url: https://review.openocd.org/gitweb?a=blobdiff_plain;f=src%2Ftarget%2Farm_opcodes.h;h=81c4766ad40355750187b139d018348941fa718c;hb=b8be5de75d021b5e01a6739fc70c793a6603467c;hp=9a48e6d03acdde0fb906de6c44f2c5185d099512;hpb=81f238f522ecba6c24217d94b17086e2d4fcce59;p=openocd.git

diff --git a/src/target/arm_opcodes.h b/src/target/arm_opcodes.h
old mode 100755
new mode 100644
index 9a48e6d03a..81c4766ad4
--- a/src/target/arm_opcodes.h
+++ b/src/target/arm_opcodes.h
@@ -24,7 +24,7 @@
  * You should have received a copy of the GNU General Public License
  * along with this program; if not, write to the
  * Free Software Foundation, Inc.,
- * 59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
  */
 #ifndef __ARM_OPCODES_H
 #define __ARM_OPCODES_H
@@ -90,8 +90,8 @@
  * Rd: register to load
  * Rn: base register
  */
-#define ARMV4_5_LDRW_IP(Rd, Rn)	(0xe4900004 | ((Rd) << 12) | ((Rn) << 16)) 
-	
+#define ARMV4_5_LDRW_IP(Rd, Rn)	(0xe4900004 | ((Rd) << 12) | ((Rn) << 16))
+
 /* Load Register Halfword Immediate Post-Index
  * Rd: register to load
  * Rn: base register
@@ -108,7 +108,7 @@
  * Rd: register to store
  * Rn: base register
  */
-#define ARMV4_5_STRW_IP(Rd, Rn)	(0xe4800004 | ((Rd) << 12) | ((Rn) << 16)) 
+#define ARMV4_5_STRW_IP(Rd, Rn)	(0xe4800004 | ((Rd) << 12) | ((Rn) << 16))
 
 /* Store register Halfword Immediate Post-Index
  * Rd: register to store
@@ -133,6 +133,36 @@
  */
 #define ARMV4_5_BX(Rm) (0xe12fff10 | (Rm))
 
+/* Store data from coprocessor to consecutive memory
+ * See Armv7-A arch doc section A8.6.187
+ * P:    1=index mode (offset from Rn)
+ * U:    1=add, 0=subtract  Rn address with imm
+ * D:    Opcode D encoding
+ * W:    write back the offset start address to the Rn register
+ * CP:   Coprocessor number (4 bits)
+ * CRd:  Coprocessor source register (4 bits)
+ * Rn:   Base register for memory address (4 bits)
+ * imm:  Immediate value (0 - 1020, must be divisible by 4)
+ */
+#define ARMV4_5_STC(P, U, D, W, CP, CRd, Rn, imm) \
+	(0xec000000 | ((P) << 24) | ((U) << 23) | ((D) << 22) | \
+	((W) << 21) | ((Rn) << 16) | ((CRd) << 12) | ((CP) << 8) | ((imm)>>2))
+
+/* Loads data from consecutive memory to coprocessor
+ * See Armv7-A arch doc section A8.6.51
+ * P:    1=index mode (offset from Rn)
+ * U:    1=add, 0=subtract  Rn address with imm
+ * D:    Opcode D encoding
+ * W:    write back the offset start address to the Rn register
+ * CP:   Coprocessor number (4 bits)
+ * CRd:  Coprocessor dest register (4 bits)
+ * Rn:   Base register for memory address (4 bits)
+ * imm:  Immediate value (0 - 1020, must be divisible by 4)
+ */
+#define ARMV4_5_LDC(P, U, D, W, CP, CRd, Rn, imm) \
+	(0xec100000 | ((P) << 24) | ((U) << 23) | ((D) << 22) | \
+	((W) << 21) | ((Rn) << 16) | ((CRd) << 12) | ((CP) << 8) | ((imm) >> 2))
+
 /* Move to ARM register from coprocessor
  * CP: Coprocessor number
  * op1: Coprocessor opcode