X-Git-Url: https://review.openocd.org/gitweb?a=blobdiff_plain;f=src%2Ftarget%2Farm_dpm.h;h=5d75ed4121f5730bada76e060a590b8d821eb658;hb=7176ed9afe0972ca768d6aabc8e58418d6f91286;hp=1f32e8bcb4d0321adf37783bed5f81d38fecfadc;hpb=eb6c880ddcb06cb011ebd4557d9057d04ab9b4fb;p=openocd.git

diff --git a/src/target/arm_dpm.h b/src/target/arm_dpm.h
index 1f32e8bcb4..5d75ed4121 100644
--- a/src/target/arm_dpm.h
+++ b/src/target/arm_dpm.h
@@ -31,24 +31,22 @@
  * registers are compatible.
  */
 
-struct dpm_bp {
-	struct breakpoint *bp;
-	/* bp->address == breakpoint value register
-	 * control == breakpoint control register
-	 */
+struct dpm_bpwp {
+	unsigned number;
+	uint32_t address;
 	uint32_t control;
 	/* true if hardware state needs flushing */
 	bool dirty;
 };
 
+struct dpm_bp {
+	struct breakpoint *bp;
+	struct dpm_bpwp bpwp;
+};
+
 struct dpm_wp {
 	struct watchpoint *wp;
-	/* wp->address == watchpoint value register
-	 * control == watchpoint control register
-	 */
-	uint32_t control;
-	/* true if hardware state needs flushing */
-	bool dirty;
+	struct dpm_bpwp bpwp;
 };
 
 /**
@@ -125,6 +123,9 @@ struct arm_dpm {
 	/** Address of the instruction which triggered a watchpoint. */
 	uint32_t wp_pc;
 
+	/** Recent value of DSCR. */
+	uint32_t dscr;
+
 	// FIXME -- read/write DCSR methods and symbols
 };
 
@@ -141,6 +142,7 @@ void arm_dpm_report_wfar(struct arm_dpm *, uint32_t wfar);
  */
 #define DSCR_CORE_HALTED	(1 << 0)
 #define DSCR_CORE_RESTARTED	(1 << 1)
+#define DSCR_INT_DIS		(1 << 11)
 #define DSCR_ITR_EN		(1 << 13)
 #define DSCR_HALT_DBG_MODE	(1 << 14)
 #define DSCR_MON_DBG_MODE	(1 << 15)
@@ -150,4 +152,6 @@ void arm_dpm_report_wfar(struct arm_dpm *, uint32_t wfar);
 
 #define DSCR_ENTRY(dscr) (((dscr) >> 2) & 0xf)
 
+void arm_dpm_report_dscr(struct arm_dpm *dpm, uint32_t dcsr);
+
 #endif /* __ARM_DPM_H */