X-Git-Url: https://review.openocd.org/gitweb?a=blobdiff_plain;f=src%2Ftarget%2Farm_dpm.h;h=135e3db86decad962de8e66188c3954a4a4abd1c;hb=cfd79e96a6436cea427245a2c2f18fd52001898b;hp=67ce2180edd65360b555cd409b10b5538c868a98;hpb=c008d30fe85a674842632e32d732e22e0a91b95d;p=openocd.git

diff --git a/src/target/arm_dpm.h b/src/target/arm_dpm.h
index 67ce2180ed..135e3db86d 100644
--- a/src/target/arm_dpm.h
+++ b/src/target/arm_dpm.h
@@ -31,6 +31,26 @@
  * registers are compatible.
  */
 
+struct dpm_bp {
+	struct breakpoint *bp;
+	/* bp->address == breakpoint value register
+	 * control == breakpoint control register
+	 */
+	uint32_t control;
+	/* true if hardware state needs flushing */
+	bool dirty;
+};
+
+struct dpm_wp {
+	struct watchpoint *wp;
+	/* wp->address == watchpoint value register
+	 * control == watchpoint control register
+	 */
+	uint32_t control;
+	/* true if hardware state needs flushing */
+	bool dirty;
+};
+
 /**
  * This wraps an implementation of DPM primitives.  Each interface
  * provider supplies a structure like this, which is the glue between
@@ -74,17 +94,66 @@ struct arm_dpm {
 	int (*instr_read_data_r0)(struct arm_dpm *,
 			uint32_t opcode, uint32_t *data);
 
-	// FIXME -- add breakpoint support
+	/* BREAKPOINT/WATCHPOINT SUPPORT */
+
+	/**
+	 * Enables one breakpoint or watchpoint by writing to the
+	 * hardware registers.  The specified breakpoint/watchpoint
+	 * must currently be disabled.  Indices 0..15 are used for
+	 * breakpoints; indices 16..31 are for watchpoints.
+	 */
+	int (*bpwp_enable)(struct arm_dpm *, unsigned index,
+			uint32_t addr, uint32_t control);
+
+	/**
+	 * Disables one breakpoint or watchpoint by clearing its
+	 * hardware control registers.  Indices are the same ones
+	 * accepted by bpwp_enable().
+	 */
+	int (*bpwp_disable)(struct arm_dpm *, unsigned index);
 
-	// FIXME -- add watchpoint support (including context-sensitive ones)
+	/* The breakpoint and watchpoint arrays are private to the
+	 * DPM infrastructure.  There are nbp indices in the dbp
+	 * array.  There are nwp indices in the dwp array.
+	 */
+
+	unsigned nbp;
+	unsigned nwp;
+	struct dpm_bp *dbp;
+	struct dpm_wp *dwp;
+
+	/** Address of the instruction which triggered a watchpoint. */
+	uint32_t wp_pc;
+
+	/** Recent value of DSCR. */
+	uint32_t dscr;
 
 	// FIXME -- read/write DCSR methods and symbols
 };
 
 int arm_dpm_setup(struct arm_dpm *dpm);
-int arm_dpm_reinitialize(struct arm_dpm *dpm);
+int arm_dpm_initialize(struct arm_dpm *dpm);
 
 int arm_dpm_read_current_registers(struct arm_dpm *);
-int arm_dpm_write_dirty_registers(struct arm_dpm *);
+int arm_dpm_write_dirty_registers(struct arm_dpm *, bool bpwp);
+
+void arm_dpm_report_wfar(struct arm_dpm *, uint32_t wfar);
+
+/* Subset of DSCR bits; see ARMv7a arch spec section C10.3.1.
+ * Not all v7 bits are valid in v6.
+ */
+#define DSCR_CORE_HALTED	(1 << 0)
+#define DSCR_CORE_RESTARTED	(1 << 1)
+#define DSCR_INT_DIS		(1 << 11)
+#define DSCR_ITR_EN		(1 << 13)
+#define DSCR_HALT_DBG_MODE	(1 << 14)
+#define DSCR_MON_DBG_MODE	(1 << 15)
+#define DSCR_INSTR_COMP		(1 << 24)
+#define DSCR_DTR_TX_FULL	(1 << 29)
+#define DSCR_DTR_RX_FULL	(1 << 30)
+
+#define DSCR_ENTRY(dscr) (((dscr) >> 2) & 0xf)
+
+void arm_dpm_report_dscr(struct arm_dpm *dpm, uint32_t dcsr);
 
 #endif /* __ARM_DPM_H */