X-Git-Url: https://review.openocd.org/gitweb?a=blobdiff_plain;f=src%2Ftarget%2Farm_disassembler.h;h=156c037e1eda42bc77ffe51b69e02535e2971580;hb=f0c0256b1f05a04a58d857e9d865a0be0dd1680d;hp=a8b9aba115938f45d59e7f1292d4432960b3c1f9;hpb=2e779198535580515dfa9c8bfe1f3fe08abdb84b;p=openocd.git

diff --git a/src/target/arm_disassembler.h b/src/target/arm_disassembler.h
index a8b9aba115..156c037e1e 100644
--- a/src/target/arm_disassembler.h
+++ b/src/target/arm_disassembler.h
@@ -20,7 +20,7 @@
 #ifndef ARM_DISASSEMBLER_H
 #define ARM_DISASSEMBLER_H
 
-#include "types.h"
+#include <helper/types.h>
 
 enum arm_instruction_type
 {
@@ -120,11 +120,11 @@ enum arm_instruction_type
 	ARM_UNDEFINED_INSTRUCTION = 0xffffffff,
 };
 
-typedef struct arm_b_bl_bx_blx_instr_s
+struct arm_b_bl_bx_blx_instr
 {
 	int reg_operand;
 	uint32_t target_address;
-} arm_b_bl_bx_blx_instr_t;
+};
 
 union arm_shifter_operand
 {
@@ -143,16 +143,16 @@ union arm_shifter_operand
 	} register_shift;
 };
 
-typedef struct arm_data_proc_instr_s
+struct arm_data_proc_instr
 {
 	int variant; /* 0: immediate, 1: immediate_shift, 2: register_shift */
 	uint8_t S;
 	uint8_t Rn;
 	uint8_t Rd;
 	union arm_shifter_operand shifter_operand;
-} arm_data_proc_instr_t;
+};
 
-typedef struct arm_load_store_instr_s
+struct arm_load_store_instr
 {
 	uint8_t Rd;
 	uint8_t Rn;
@@ -168,35 +168,42 @@ typedef struct arm_load_store_instr_s
 			uint8_t shift_imm;
 		} reg;
 	} offset;
-} arm_load_store_instr_t;
+};
 
-typedef struct arm_load_store_multiple_instr_s
+struct arm_load_store_multiple_instr
 {
 	uint8_t Rn;
 	uint32_t register_list;
 	uint8_t addressing_mode; /* 0: IA, 1: IB, 2: DA, 3: DB */
 	uint8_t S;
 	uint8_t W;
-} arm_load_store_multiple_instr_t;
+};
 
-typedef struct arm_instruction_s
+struct arm_instruction
 {
 	enum arm_instruction_type type;
 	char text[128];
 	uint32_t opcode;
 
+	/* return value ... Thumb-2 sizes vary */
+	unsigned instruction_size;
+
 	union {
-		arm_b_bl_bx_blx_instr_t b_bl_bx_blx;
-		arm_data_proc_instr_t data_proc;
-		arm_load_store_instr_t load_store;
-		arm_load_store_multiple_instr_t load_store_multiple;
+		struct arm_b_bl_bx_blx_instr b_bl_bx_blx;
+		struct arm_data_proc_instr data_proc;
+		struct arm_load_store_instr load_store;
+		struct arm_load_store_multiple_instr load_store_multiple;
 	} info;
 
-} arm_instruction_t;
+};
 
-extern int arm_evaluate_opcode(uint32_t opcode, uint32_t address, arm_instruction_t *instruction);
-extern int thumb_evaluate_opcode(uint16_t opcode, uint32_t address, arm_instruction_t *instruction);
-extern int arm_access_size(arm_instruction_t *instruction);
+int arm_evaluate_opcode(uint32_t opcode, uint32_t address,
+		struct arm_instruction *instruction);
+int thumb_evaluate_opcode(uint16_t opcode, uint32_t address,
+		struct arm_instruction *instruction);
+int thumb2_opcode(struct target *target, uint32_t address,
+		struct arm_instruction *instruction);
+int arm_access_size(struct arm_instruction *instruction);
 
 #define COND(opcode) (arm_condition_strings[(opcode & 0xf0000000) >> 28])