X-Git-Url: https://review.openocd.org/gitweb?a=blobdiff_plain;f=src%2Ftarget%2Farm_disassembler.c;h=b93df64d10b2f5fd8a8824c06f1909f2e4a0ef2d;hb=30f6142fc8570549ff42676ffe16425c6a6ef264;hp=ce338859424d614dba1e2afe7bad7c82b8963a1f;hpb=55edfdf2ab6c5d1d6cd4c1c97a79cbb1d39b1f22;p=openocd.git

diff --git a/src/target/arm_disassembler.c b/src/target/arm_disassembler.c
index ce33885942..b93df64d10 100644
--- a/src/target/arm_disassembler.c
+++ b/src/target/arm_disassembler.c
@@ -1784,8 +1784,12 @@ static int evaluate_b_bl_blx_thumb(uint16_t opcode,
 	}
 
 	/* TODO: deal correctly with dual opcode (prefixed) BL/BLX;
-	 * these are effectively 32-bit instructions even in Thumb1.
-	 * Might be simplest to always use the Thumb2 decoder.
+	 * these are effectively 32-bit instructions even in Thumb1.  For
+	 * disassembly, it's simplest to always use the Thumb2 decoder.
+	 *
+	 * But some cores will evidently handle them as two instructions,
+	 * where exceptions may occur between the two.  The ETMv3.2+ ID
+	 * register has a bit which exposes this behavior.
 	 */
 
 	snprintf(instruction->text, 128,
@@ -4191,7 +4195,7 @@ ldrh_literal:
  * always set.  That means eventual arm_simulate_step() support for Thumb2
  * will need work in this area.
  */
-int thumb2_opcode(target_t *target, uint32_t address, struct arm_instruction *instruction)
+int thumb2_opcode(struct target *target, uint32_t address, struct arm_instruction *instruction)
 {
 	int retval;
 	uint16_t op;