X-Git-Url: https://review.openocd.org/gitweb?a=blobdiff_plain;f=src%2Ftarget%2Farm_adi_v5.h;h=7c27d609411c447a6a1eaf76287c3f8757b4bc4f;hb=c3c15d2e076639fad185a0c45b866e9c5e754af5;hp=1c4b1000c55644187497f336fbbe8fd44d0a594e;hpb=c560d9d31b3f46677509246efb2d01a8834944f8;p=openocd.git diff --git a/src/target/arm_adi_v5.h b/src/target/arm_adi_v5.h index 1c4b1000c5..7c27d60941 100644 --- a/src/target/arm_adi_v5.h +++ b/src/target/arm_adi_v5.h @@ -31,14 +31,9 @@ * resources accessed through a MEM-AP. */ +#include #include "arm_jtag.h" -/* FIXME remove these JTAG-specific decls when mem_ap_read_buf_u32() - * is no longer JTAG-specific - */ -#define JTAG_DP_DPACC 0xA -#define JTAG_DP_APACC 0xB - /* three-bit ACK values for SWD access (sent LSB first) */ #define SWD_ACK_OK 0x1 #define SWD_ACK_WAIT 0x2 @@ -122,83 +117,59 @@ #define CSW_SPROT (1UL << 30) #define CSW_DBGSWENABLE (1UL << 31) -/** - * This represents an ARM Debug Interface (v5) Debug Access Port (DAP). - * A DAP has two types of component: one Debug Port (DP), which is a - * transport agent; and at least one Access Port (AP), controlling - * resource access. Most common is a MEM-AP, for memory access. - * - * There are two basic DP transports: JTAG, and ARM's low pin-count SWD. - * Accordingly, this interface is responsible for hiding the transport - * differences so upper layer code can largely ignore them. - * - * When the chip is implemented with JTAG-DP or SW-DP, the transport is - * fixed as JTAG or SWD, respectively. Chips incorporating SWJ-DP permit - * a choice made at board design time (by only using the SWD pins), or - * as part of setting up a debug session (if all the dual-role JTAG/SWD - * signals are available). - */ -struct adiv5_dap { - const struct dap_ops *ops; +/* Fields of the MEM-AP's IDR register */ +#define IDR_REV (0xFUL << 28) +#define IDR_JEP106 (0x7FFUL << 17) +#define IDR_CLASS (0xFUL << 13) +#define IDR_VARIANT (0xFUL << 4) +#define IDR_TYPE (0xFUL << 0) - struct arm_jtag *jtag_info; - /* Control config */ - uint32_t dp_ctrl_stat; +#define IDR_JEP106_ARM 0x04760000 - uint32_t apcsw[256]; - uint32_t apsel; +#define DP_SELECT_APSEL 0xFF000000 +#define DP_SELECT_APBANK 0x000000F0 +#define DP_SELECT_DPBANK 0x0000000F +#define DP_SELECT_INVALID 0x00FFFF00 /* Reserved bits one */ +/** + * This represents an ARM Debug Interface (v5) Access Port (AP). + * Most common is a MEM-AP, for memory access. + */ +struct adiv5_ap { /** - * Cache for DP_SELECT bits identifying the current AP. A DAP may - * connect to multiple APs, such as one MEM-AP for general access, - * another reserved for accessing debug modules, and a JTAG-DP. - * "-1" indicates no cached value. + * DAP this AP belongs to. */ - uint32_t ap_current; + struct adiv5_dap *dap; /** - * Cache for DP_SELECT bits identifying the current four-word AP - * register bank. This caches AP register addresss bits 7:4; JTAG - * and SWD access primitves pass address bits 3:2; bits 1:0 are zero. - * "-1" indicates no cached value. + * Number of this AP. */ - uint32_t ap_bank_value; + uint8_t ap_num; /** - * Cache for DP_SELECT bits identifying the current four-word DP - * register bank. This caches DP register addresss bits 7:4; JTAG - * and SWD access primitves pass address bits 3:2; bits 1:0 are zero. + * Default value for (MEM-AP) AP_REG_CSW register. */ - uint32_t dp_bank_value; + uint32_t csw_default; /** * Cache for (MEM-AP) AP_REG_CSW register value. This is written to * configure an access mode, such as autoincrementing AP_REG_TAR during * word access. "-1" indicates no cached value. */ - uint32_t ap_csw_value; + uint32_t csw_value; /** * Cache for (MEM-AP) AP_REG_TAR register value This is written to * configure the address being read or written * "-1" indicates no cached value. */ - uint32_t ap_tar_value; - - /* information about current pending SWjDP-AHBAP transaction */ - uint8_t ack; - - /** - * Holds the pointer to the destination word for the last queued read, - * for use with posted AP read sequence optimization. - */ - uint32_t *last_read; + uint32_t tar_value; /** * Configures how many extra tck clocks are added after starting a * MEM-AP access before we try to read its status (and/or result). */ - uint32_t memaccess_tck; + uint32_t memaccess_tck; /* Size of TAR autoincrement block, ARM ADI Specification requires at least 10 bits */ uint32_t tar_autoincr_block; @@ -208,6 +179,54 @@ struct adiv5_dap { /* true if unaligned memory access is not supported by the MEM-AP */ bool unaligned_access_bad; +}; + + +/** + * This represents an ARM Debug Interface (v5) Debug Access Port (DAP). + * A DAP has two types of component: one Debug Port (DP), which is a + * transport agent; and at least one Access Port (AP), controlling + * resource access. + * + * There are two basic DP transports: JTAG, and ARM's low pin-count SWD. + * Accordingly, this interface is responsible for hiding the transport + * differences so upper layer code can largely ignore them. + * + * When the chip is implemented with JTAG-DP or SW-DP, the transport is + * fixed as JTAG or SWD, respectively. Chips incorporating SWJ-DP permit + * a choice made at board design time (by only using the SWD pins), or + * as part of setting up a debug session (if all the dual-role JTAG/SWD + * signals are available). + */ +struct adiv5_dap { + const struct dap_ops *ops; + + /* dap transaction list for WAIT support */ + struct list_head cmd_journal; + + struct jtag_tap *tap; + /* Control config */ + uint32_t dp_ctrl_stat; + + struct adiv5_ap ap[256]; + + /* The current manually selected AP by the "dap apsel" command */ + uint32_t apsel; + + /** + * Cache for DP_SELECT register. A value of DP_SELECT_INVALID + * indicates no cached value and forces rewrite of the register. + */ + uint32_t select; + + /* information about current pending SWjDP-AHBAP transaction */ + uint8_t ack; + + /** + * Holds the pointer to the destination word for the last queued read, + * for use with posted AP read sequence optimization. + */ + uint32_t *last_read; /* The TI TMS470 and TMS570 series processors use a BE-32 memory ordering * despite lack of support in the ARMv7 architecture. Memory access through @@ -230,11 +249,6 @@ struct adiv5_dap { * available until run(). */ struct dap_ops { - /** If the DAP transport isn't SWD, it must be JTAG. Upper level - * code may need to care about the difference in some cases. - */ - bool is_swd; - /** DP register read. */ int (*queue_dp_read)(struct adiv5_dap *dap, unsigned reg, uint32_t *data); @@ -243,10 +257,10 @@ struct dap_ops { uint32_t data); /** AP register read. */ - int (*queue_ap_read)(struct adiv5_dap *dap, unsigned reg, + int (*queue_ap_read)(struct adiv5_ap *ap, unsigned reg, uint32_t *data); /** AP register write. */ - int (*queue_ap_write)(struct adiv5_dap *dap, unsigned reg, + int (*queue_ap_write)(struct adiv5_ap *ap, unsigned reg, uint32_t data); /** AP operation abort. */ @@ -254,15 +268,28 @@ struct dap_ops { /** Executes all queued DAP operations. */ int (*run)(struct adiv5_dap *dap); + + /** Executes all queued DAP operations but doesn't check + * sticky error conditions */ + int (*sync)(struct adiv5_dap *dap); +}; + +/* + * Access Port classes + */ +enum ap_class { + AP_CLASS_NONE = 0x00000, /* No class defined */ + AP_CLASS_MEM_AP = 0x10000, /* MEM-AP */ }; /* * Access Port types */ enum ap_type { - AP_TYPE_AHB_AP = 0x01, /* AHB Memory-AP */ - AP_TYPE_APB_AP = 0x02, /* APB Memory-AP */ - AP_TYPE_JTAG_AP = 0x10 /* JTAG-AP - JTAG master for controlling other JTAG devices */ + AP_TYPE_JTAG_AP = 0x0, /* JTAG-AP - JTAG master for controlling other JTAG devices */ + AP_TYPE_AHB_AP = 0x1, /* AHB Memory-AP */ + AP_TYPE_APB_AP = 0x2, /* APB Memory-AP */ + AP_TYPE_AXI_AP = 0x4, /* AXI Memory-AP */ }; /** @@ -305,34 +332,34 @@ static inline int dap_queue_dp_write(struct adiv5_dap *dap, /** * Queue an AP register read. * - * @param dap The DAP used for reading. + * @param ap The AP used for reading. * @param reg The number of the AP register being read. * @param data Pointer saying where to store the register's value * (in host endianness). * * @return ERROR_OK for success, else a fault code. */ -static inline int dap_queue_ap_read(struct adiv5_dap *dap, +static inline int dap_queue_ap_read(struct adiv5_ap *ap, unsigned reg, uint32_t *data) { - assert(dap->ops != NULL); - return dap->ops->queue_ap_read(dap, reg, data); + assert(ap->dap->ops != NULL); + return ap->dap->ops->queue_ap_read(ap, reg, data); } /** * Queue an AP register write. * - * @param dap The DAP used for writing. + * @param ap The AP used for writing. * @param reg The number of the AP register being written. * @param data Value being written (host endianness) * * @return ERROR_OK for success, else a fault code. */ -static inline int dap_queue_ap_write(struct adiv5_dap *dap, +static inline int dap_queue_ap_write(struct adiv5_ap *ap, unsigned reg, uint32_t data) { - assert(dap->ops != NULL); - return dap->ops->queue_ap_write(dap, reg, data); + assert(ap->dap->ops != NULL); + return ap->dap->ops->queue_ap_write(ap, reg, data); } /** @@ -368,6 +395,14 @@ static inline int dap_run(struct adiv5_dap *dap) return dap->ops->run(dap); } +static inline int dap_sync(struct adiv5_dap *dap) +{ + assert(dap->ops != NULL); + if (dap->ops->sync) + return dap->ops->sync(dap); + return ERROR_OK; +} + static inline int dap_dp_read_atomic(struct adiv5_dap *dap, unsigned reg, uint32_t *value) { @@ -409,74 +444,53 @@ static inline int dap_dp_poll_register(struct adiv5_dap *dap, unsigned reg, } } -/** Accessor for currently selected DAP-AP number (0..255) */ -static inline uint8_t dap_ap_get_select(struct adiv5_dap *swjdp) -{ - return (uint8_t)(swjdp->ap_current >> 24); -} - -/* AP selection applies to future AP transactions */ -void dap_ap_select(struct adiv5_dap *dap, uint8_t ap); - -/* Queued AP transactions */ -int dap_setup_accessport(struct adiv5_dap *swjdp, - uint32_t csw, uint32_t tar); - -/* Queued MEM-AP memory mapped single word transfers */ -int mem_ap_read_u32(struct adiv5_dap *swjdp, uint32_t address, uint32_t *value); -int mem_ap_write_u32(struct adiv5_dap *swjdp, uint32_t address, uint32_t value); - -/* Synchronous MEM-AP memory mapped single word transfers */ -int mem_ap_read_atomic_u32(struct adiv5_dap *swjdp, - uint32_t address, uint32_t *value); -int mem_ap_write_atomic_u32(struct adiv5_dap *swjdp, - uint32_t address, uint32_t value); - -/* Queued MEM-AP memory mapped single word transfers with selection of ap */ -int mem_ap_sel_read_u32(struct adiv5_dap *swjdp, uint8_t ap, +/* Queued MEM-AP memory mapped single word transfers. */ +int mem_ap_read_u32(struct adiv5_ap *ap, uint32_t address, uint32_t *value); -int mem_ap_sel_write_u32(struct adiv5_dap *swjdp, uint8_t ap, +int mem_ap_write_u32(struct adiv5_ap *ap, uint32_t address, uint32_t value); -/* Synchronous MEM-AP memory mapped single word transfers with selection of ap */ -int mem_ap_sel_read_atomic_u32(struct adiv5_dap *swjdp, uint8_t ap, +/* Synchronous MEM-AP memory mapped single word transfers. */ +int mem_ap_read_atomic_u32(struct adiv5_ap *ap, uint32_t address, uint32_t *value); -int mem_ap_sel_write_atomic_u32(struct adiv5_dap *swjdp, uint8_t ap, +int mem_ap_write_atomic_u32(struct adiv5_ap *ap, uint32_t address, uint32_t value); -/* Synchronous MEM-AP memory mapped bus block transfers */ -int mem_ap_read(struct adiv5_dap *dap, uint8_t *buffer, uint32_t size, - uint32_t count, uint32_t address, bool addrinc); -int mem_ap_write(struct adiv5_dap *dap, const uint8_t *buffer, uint32_t size, - uint32_t count, uint32_t address, bool addrinc); - -/* Synchronous MEM-AP memory mapped bus block transfers with selection of ap */ -int mem_ap_sel_read_buf(struct adiv5_dap *swjdp, uint8_t ap, +/* Synchronous MEM-AP memory mapped bus block transfers. */ +int mem_ap_read_buf(struct adiv5_ap *ap, uint8_t *buffer, uint32_t size, uint32_t count, uint32_t address); -int mem_ap_sel_write_buf(struct adiv5_dap *swjdp, uint8_t ap, +int mem_ap_write_buf(struct adiv5_ap *ap, const uint8_t *buffer, uint32_t size, uint32_t count, uint32_t address); -/* Synchronous, non-incrementing buffer functions for accessing fifos, with - * selection of ap */ -int mem_ap_sel_read_buf_noincr(struct adiv5_dap *swjdp, uint8_t ap, +/* Synchronous, non-incrementing buffer functions for accessing fifos. */ +int mem_ap_read_buf_noincr(struct adiv5_ap *ap, uint8_t *buffer, uint32_t size, uint32_t count, uint32_t address); -int mem_ap_sel_write_buf_noincr(struct adiv5_dap *swjdp, uint8_t ap, +int mem_ap_write_buf_noincr(struct adiv5_ap *ap, const uint8_t *buffer, uint32_t size, uint32_t count, uint32_t address); +/* Create DAP struct */ +struct adiv5_dap *dap_init(void); + /* Initialisation of the debug system, power domains and registers */ -int ahbap_debugport_init(struct adiv5_dap *swjdp); +int dap_dp_init(struct adiv5_dap *dap); +int mem_ap_init(struct adiv5_ap *ap); /* Probe the AP for ROM Table location */ -int dap_get_debugbase(struct adiv5_dap *dap, int ap, +int dap_get_debugbase(struct adiv5_ap *ap, uint32_t *dbgbase, uint32_t *apid); /* Probe Access Ports to find a particular type */ int dap_find_ap(struct adiv5_dap *dap, enum ap_type type_to_find, - uint8_t *ap_num_out); + struct adiv5_ap **ap_out); + +static inline struct adiv5_ap *dap_ap(struct adiv5_dap *dap, uint8_t ap_num) +{ + return &dap->ap[ap_num]; +} /* Lookup CoreSight component */ -int dap_lookup_cs_component(struct adiv5_dap *dap, int ap, +int dap_lookup_cs_component(struct adiv5_ap *ap, uint32_t dbgbase, uint8_t type, uint32_t *addr, int32_t *idx); struct target;