X-Git-Url: https://review.openocd.org/gitweb?a=blobdiff_plain;f=src%2Ftarget%2Farm_adi_v5.c;h=408956784cd5707f7007daaaeccb997e3b832379;hb=82f2492138e053d5e3577e83b80cab8d41c0d08b;hp=72408e1e68fe8666975aff3a40879f477d16b252;hpb=21378f58b604453262ac6f3cbf3d6b94b50251cf;p=openocd.git diff --git a/src/target/arm_adi_v5.c b/src/target/arm_adi_v5.c index 72408e1e68..408956784c 100644 --- a/src/target/arm_adi_v5.c +++ b/src/target/arm_adi_v5.c @@ -7,7 +7,9 @@ * * * Copyright (C) 2009 by Oyvind Harboe * * oyvind.harboe@zylin.com * - * * + * * + * Copyright (C) 2009-2010 by David Brownell * + * * * This program is free software; you can redistribute it and/or modify * * it under the terms of the GNU General Public License as published by * * the Free Software Foundation; either version 2 of the License, or * @@ -23,23 +25,41 @@ * Free Software Foundation, Inc., * * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. * ***************************************************************************/ -/*************************************************************************** - * * - * This file implements support for the ARM Debug Interface v5 (ADI_V5) * - * * - * ARM(tm) Debug Interface v5 Architecture Specification ARM IHI 0031A * - * * - * CoreSight(tm) DAP-Lite TRM, ARM DDI 0316D * - * Cortex-M3(tm) TRM, ARM DDI 0337G * - * * -***************************************************************************/ + +/** + * @file + * This file implements support for the ARM Debug Interface version 5 (ADIv5) + * debugging architecture. Compared with previous versions, this includes + * a low pin-count Serial Wire Debug (SWD) alternative to JTAG for message + * transport, and focusses on memory mapped resources as defined by the + * CoreSight architecture. + * + * A key concept in ADIv5 is the Debug Access Port, or DAP. A DAP has two + * basic components: a Debug Port (DP) transporting messages to and from a + * debugger, and an Access Port (AP) accessing resources. Three types of DP + * are defined. One uses only JTAG for communication, and is called JTAG-DP. + * One uses only SWD for communication, and is called SW-DP. The third can + * use either SWD or JTAG, and is called SWJ-DP. The most common type of AP + * is used to access memory mapped resources and is called a MEM-AP. Also a + * JTAG-AP is also defined, bridging to JTAG resources; those are uncommon. + */ + +/* + * Relevant specifications from ARM include: + * + * ARM(tm) Debug Interface v5 Architecture Specification ARM IHI 0031A + * CoreSight(tm) v1.0 Architecture Specification ARM IHI 0029B + * + * CoreSight(tm) DAP-Lite TRM, ARM DDI 0316D + * Cortex-M3(tm) TRM, ARM DDI 0337G + */ #ifdef HAVE_CONFIG_H #include "config.h" #endif #include "arm_adi_v5.h" -#include "time_support.h" +#include /* * Transaction Mode: @@ -70,8 +90,27 @@ static uint32_t max_tar_block_size(uint32_t tar_autoincr_block, uint32_t address * * ***************************************************************************/ -/* Scan out and in from target ordered uint8_t buffers */ -int adi_jtag_dp_scan(struct swjdp_common *swjdp, uint8_t instr, uint8_t reg_addr, uint8_t RnW, uint8_t *outvalue, uint8_t *invalue, uint8_t *ack) +/** + * Scan DPACC or APACC using target ordered uint8_t buffers. No endianness + * conversions are performed. See section 4.4.3 of the ADIv5 spec, which + * discusses operations which access these registers. + * + * Note that only one scan is performed. If RnW is set, a separate scan + * will be needed to collect the data which was read; the "invalue" collects + * the posted result of a preceding operation, not the current one. + * + * @param swjdp the DAP + * @param instr JTAG_DP_APACC (AP access) or JTAG_DP_DPACC (DP access) + * @param reg_addr two significant bits; A[3:2]; for APACC access, the + * SELECT register has more addressing bits. + * @param RnW false iff outvalue will be written to the DP or AP + * @param outvalue points to a 32-bit (little-endian) integer + * @param invalue NULL, or points to a 32-bit (little-endian) integer + * @param ack points to where the three bit JTAG_ACK_* code will be stored + */ +static int adi_jtag_dp_scan(struct swjdp_common *swjdp, + uint8_t instr, uint8_t reg_addr, uint8_t RnW, + uint8_t *outvalue, uint8_t *invalue, uint8_t *ack) { struct arm_jtag *jtag_info = swjdp->jtag_info; struct scan_field fields[2]; @@ -81,15 +120,31 @@ int adi_jtag_dp_scan(struct swjdp_common *swjdp, uint8_t instr, uint8_t reg_addr arm_jtag_set_instr(jtag_info, instr, NULL); /* Add specified number of tck clocks before accessing memory bus */ - if ((instr == DAP_IR_APACC) && ((reg_addr == AP_REG_DRW)||((reg_addr&0xF0) == AP_REG_BD0))&& (swjdp->memaccess_tck != 0)) + + /* REVISIT these TCK cycles should be *AFTER* updating APACC, since + * they provide more time for the (MEM) AP to complete the read ... + * See "Minimum Response Time" for JTAG-DP, in the ADIv5 spec. + */ + if ((instr == JTAG_DP_APACC) + && ((reg_addr == AP_REG_DRW) + || ((reg_addr & 0xF0) == AP_REG_BD0)) + && (swjdp->memaccess_tck != 0)) jtag_add_runtest(swjdp->memaccess_tck, jtag_set_end_state(TAP_IDLE)); + /* Scan out a read or write operation using some DP or AP register. + * For APACC access with any sticky error flag set, this is discarded. + */ fields[0].tap = jtag_info->tap; fields[0].num_bits = 3; buf_set_u32(&out_addr_buf, 0, 3, ((reg_addr >> 1) & 0x6) | (RnW & 0x1)); fields[0].out_value = &out_addr_buf; fields[0].in_value = ack; + /* NOTE: if we receive JTAG_ACK_WAIT, the previous operation did not + * complete; data we write is discarded, data we read is unpredictable. + * When overrun detect is active, STICKYORUN is set. + */ + fields[1].tap = jtag_info->tap; fields[1].num_bits = 32; fields[1].out_value = outvalue; @@ -101,7 +156,9 @@ int adi_jtag_dp_scan(struct swjdp_common *swjdp, uint8_t instr, uint8_t reg_addr } /* Scan out and in from host ordered uint32_t variables */ -int adi_jtag_dp_scan_u32(struct swjdp_common *swjdp, uint8_t instr, uint8_t reg_addr, uint8_t RnW, uint32_t outvalue, uint32_t *invalue, uint8_t *ack) +static int adi_jtag_dp_scan_u32(struct swjdp_common *swjdp, + uint8_t instr, uint8_t reg_addr, uint8_t RnW, + uint32_t outvalue, uint32_t *invalue, uint8_t *ack) { struct arm_jtag *jtag_info = swjdp->jtag_info; struct scan_field fields[2]; @@ -112,7 +169,14 @@ int adi_jtag_dp_scan_u32(struct swjdp_common *swjdp, uint8_t instr, uint8_t reg_ arm_jtag_set_instr(jtag_info, instr, NULL); /* Add specified number of tck clocks before accessing memory bus */ - if ((instr == DAP_IR_APACC) && ((reg_addr == AP_REG_DRW)||((reg_addr&0xF0) == AP_REG_BD0))&& (swjdp->memaccess_tck != 0)) + + /* REVISIT these TCK cycles should be *AFTER* updating APACC, since + * they provide more time for the (MEM) AP to complete the read ... + */ + if ((instr == JTAG_DP_APACC) + && ((reg_addr == AP_REG_DRW) + || ((reg_addr & 0xF0) == AP_REG_BD0)) + && (swjdp->memaccess_tck != 0)) jtag_add_runtest(swjdp->memaccess_tck, jtag_set_end_state(TAP_IDLE)); fields[0].tap = jtag_info->tap; @@ -143,43 +207,51 @@ int adi_jtag_dp_scan_u32(struct swjdp_common *swjdp, uint8_t instr, uint8_t reg_ } /* scan_inout_check adds one extra inscan for DPAP_READ commands to read variables */ -int scan_inout_check(struct swjdp_common *swjdp, uint8_t instr, uint8_t reg_addr, uint8_t RnW, uint8_t *outvalue, uint8_t *invalue) +static int scan_inout_check(struct swjdp_common *swjdp, + uint8_t instr, uint8_t reg_addr, uint8_t RnW, + uint8_t *outvalue, uint8_t *invalue) { adi_jtag_dp_scan(swjdp, instr, reg_addr, RnW, outvalue, NULL, NULL); if ((RnW == DPAP_READ) && (invalue != NULL)) - { - adi_jtag_dp_scan(swjdp, DAP_IR_DPACC, DP_RDBUFF, DPAP_READ, 0, invalue, &swjdp->ack); - } + adi_jtag_dp_scan(swjdp, JTAG_DP_DPACC, + DP_RDBUFF, DPAP_READ, 0, invalue, &swjdp->ack); - /* In TRANS_MODE_ATOMIC all DAP_IR_APACC transactions wait for ack = OK/FAULT and the check CTRL_STAT */ - if ((instr == DAP_IR_APACC) && (swjdp->trans_mode == TRANS_MODE_ATOMIC)) - { - return swjdp_transaction_endcheck(swjdp); - } + /* In TRANS_MODE_ATOMIC all JTAG_DP_APACC transactions wait for + * ack = OK/FAULT and the check CTRL_STAT + */ + if ((instr == JTAG_DP_APACC) + && (swjdp->trans_mode == TRANS_MODE_ATOMIC)) + return jtagdp_transaction_endcheck(swjdp); return ERROR_OK; } -int scan_inout_check_u32(struct swjdp_common *swjdp, uint8_t instr, uint8_t reg_addr, uint8_t RnW, uint32_t outvalue, uint32_t *invalue) +static int scan_inout_check_u32(struct swjdp_common *swjdp, + uint8_t instr, uint8_t reg_addr, uint8_t RnW, + uint32_t outvalue, uint32_t *invalue) { + /* Issue the read or write */ adi_jtag_dp_scan_u32(swjdp, instr, reg_addr, RnW, outvalue, NULL, NULL); + /* For reads, collect posted value; RDBUFF has no other effect. + * Assumes read gets acked with OK/FAULT, and CTRL_STAT says "OK". + */ if ((RnW == DPAP_READ) && (invalue != NULL)) - { - adi_jtag_dp_scan_u32(swjdp, DAP_IR_DPACC, DP_RDBUFF, DPAP_READ, 0, invalue, &swjdp->ack); - } + adi_jtag_dp_scan_u32(swjdp, JTAG_DP_DPACC, + DP_RDBUFF, DPAP_READ, 0, invalue, &swjdp->ack); - /* In TRANS_MODE_ATOMIC all DAP_IR_APACC transactions wait for ack = OK/FAULT and then check CTRL_STAT */ - if ((instr == DAP_IR_APACC) && (swjdp->trans_mode == TRANS_MODE_ATOMIC)) - { - return swjdp_transaction_endcheck(swjdp); - } + /* In TRANS_MODE_ATOMIC all JTAG_DP_APACC transactions wait for + * ack = OK/FAULT and then check CTRL_STAT + */ + if ((instr == JTAG_DP_APACC) + && (swjdp->trans_mode == TRANS_MODE_ATOMIC)) + return jtagdp_transaction_endcheck(swjdp); return ERROR_OK; } -int swjdp_transaction_endcheck(struct swjdp_common *swjdp) +int jtagdp_transaction_endcheck(struct swjdp_common *swjdp) { int retval; uint32_t ctrlstat; @@ -188,7 +260,8 @@ int swjdp_transaction_endcheck(struct swjdp_common *swjdp) #if 0 /* Danger!!!! BROKEN!!!! */ - scan_inout_check_u32(swjdp, DAP_IR_DPACC, DP_CTRL_STAT, DPAP_READ, 0, &ctrlstat); + scan_inout_check_u32(swjdp, JTAG_DP_DPACC, + DP_CTRL_STAT, DPAP_READ, 0, &ctrlstat); /* Danger!!!! BROKEN!!!! Why will jtag_execute_queue() fail here???? R956 introduced the check on return value here and now Michael Schwingen reports that this code no longer works.... @@ -202,75 +275,103 @@ int swjdp_transaction_endcheck(struct swjdp_common *swjdp) /* Why??? second time it works??? */ #endif - scan_inout_check_u32(swjdp, DAP_IR_DPACC, DP_CTRL_STAT, DPAP_READ, 0, &ctrlstat); + /* Post CTRL/STAT read; discard any previous posted read value + * but collect its ACK status. + */ + scan_inout_check_u32(swjdp, JTAG_DP_DPACC, + DP_CTRL_STAT, DPAP_READ, 0, &ctrlstat); if ((retval = jtag_execute_queue()) != ERROR_OK) return retval; swjdp->ack = swjdp->ack & 0x7; - if (swjdp->ack != 2) + /* common code path avoids calling timeval_ms() */ + if (swjdp->ack != JTAG_ACK_OK_FAULT) { long long then = timeval_ms(); - while (swjdp->ack != 2) + + while (swjdp->ack != JTAG_ACK_OK_FAULT) { - if (swjdp->ack == 1) + if (swjdp->ack == JTAG_ACK_WAIT) { if ((timeval_ms()-then) > 1000) { - LOG_WARNING("Timeout (1000ms) waiting for ACK = OK/FAULT in SWJDP transaction"); + /* NOTE: this would be a good spot + * to use JTAG_DP_ABORT. + */ + LOG_WARNING("Timeout (1000ms) waiting " + "for ACK=OK/FAULT " + "in JTAG-DP transaction"); return ERROR_JTAG_DEVICE_ERROR; } } else { - LOG_WARNING("Invalid ACK in SWJDP transaction"); + LOG_WARNING("Invalid ACK %#x " + "in JTAG-DP transaction", + swjdp->ack); return ERROR_JTAG_DEVICE_ERROR; } - scan_inout_check_u32(swjdp, DAP_IR_DPACC, DP_CTRL_STAT, DPAP_READ, 0, &ctrlstat); + scan_inout_check_u32(swjdp, JTAG_DP_DPACC, + DP_CTRL_STAT, DPAP_READ, 0, &ctrlstat); if ((retval = jtag_execute_queue()) != ERROR_OK) return retval; swjdp->ack = swjdp->ack & 0x7; } - } else - { - /* common code path avoids fn to timeval_ms() */ } + /* REVISIT also STICKYCMP, for pushed comparisons (nyet used) */ + /* Check for STICKYERR and STICKYORUN */ if (ctrlstat & (SSTICKYORUN | SSTICKYERR)) { - LOG_DEBUG("swjdp: CTRL/STAT error 0x%" PRIx32 "", ctrlstat); + LOG_DEBUG("jtag-dp: CTRL/STAT error, 0x%" PRIx32, ctrlstat); /* Check power to debug regions */ if ((ctrlstat & 0xf0000000) != 0xf0000000) - { ahbap_debugport_init(swjdp); - } else { uint32_t mem_ap_csw, mem_ap_tar; - /* Print information about last AHBAP access */ - LOG_ERROR("AHBAP Cached values: dp_select 0x%" PRIx32 ", ap_csw 0x%" PRIx32 ", ap_tar 0x%" PRIx32 "", swjdp->dp_select_value, swjdp->ap_csw_value, swjdp->ap_tar_value); + /* Maybe print information about last intended + * MEM-AP access; but not if autoincrementing. + * *Real* CSW and TAR values are always shown. + */ + if (swjdp->ap_tar_value != (uint32_t) -1) + LOG_DEBUG("MEM-AP Cached values: " + "ap_bank 0x%" PRIx32 + ", ap_csw 0x%" PRIx32 + ", ap_tar 0x%" PRIx32, + swjdp->dp_select_value, + swjdp->ap_csw_value, + swjdp->ap_tar_value); + if (ctrlstat & SSTICKYORUN) - LOG_ERROR("SWJ-DP OVERRUN - check clock or reduce jtag speed"); + LOG_ERROR("JTAG-DP OVERRUN - check clock, " + "memaccess, or reduce jtag speed"); if (ctrlstat & SSTICKYERR) - LOG_ERROR("SWJ-DP STICKY ERROR"); + LOG_ERROR("JTAG-DP STICKY ERROR"); /* Clear Sticky Error Bits */ - scan_inout_check_u32(swjdp, DAP_IR_DPACC, DP_CTRL_STAT, DPAP_WRITE, swjdp->dp_ctrl_stat | SSTICKYORUN | SSTICKYERR, NULL); - scan_inout_check_u32(swjdp, DAP_IR_DPACC, DP_CTRL_STAT, DPAP_READ, 0, &ctrlstat); + scan_inout_check_u32(swjdp, JTAG_DP_DPACC, + DP_CTRL_STAT, DPAP_WRITE, + swjdp->dp_ctrl_stat | SSTICKYORUN + | SSTICKYERR, NULL); + scan_inout_check_u32(swjdp, JTAG_DP_DPACC, + DP_CTRL_STAT, DPAP_READ, 0, &ctrlstat); if ((retval = jtag_execute_queue()) != ERROR_OK) return retval; - LOG_DEBUG("swjdp: status 0x%" PRIx32 "", ctrlstat); + LOG_DEBUG("jtag-dp: CTRL/STAT 0x%" PRIx32, ctrlstat); dap_ap_read_reg_u32(swjdp, AP_REG_CSW, &mem_ap_csw); dap_ap_read_reg_u32(swjdp, AP_REG_TAR, &mem_ap_tar); if ((retval = jtag_execute_queue()) != ERROR_OK) return retval; - LOG_ERROR("Read MEM_AP_CSW 0x%" PRIx32 ", MEM_AP_TAR 0x%" PRIx32 "", mem_ap_csw, mem_ap_tar); + LOG_ERROR("MEM_AP_CSW 0x%" PRIx32 ", MEM_AP_TAR 0x%" + PRIx32, mem_ap_csw, mem_ap_tar); } if ((retval = jtag_execute_queue()) != ERROR_OK) @@ -287,14 +388,18 @@ int swjdp_transaction_endcheck(struct swjdp_common *swjdp) * * ***************************************************************************/ -int dap_dp_write_reg(struct swjdp_common *swjdp, uint32_t value, uint8_t reg_addr) +static int dap_dp_write_reg(struct swjdp_common *swjdp, + uint32_t value, uint8_t reg_addr) { - return scan_inout_check_u32(swjdp, DAP_IR_DPACC, reg_addr, DPAP_WRITE, value, NULL); + return scan_inout_check_u32(swjdp, JTAG_DP_DPACC, + reg_addr, DPAP_WRITE, value, NULL); } -int dap_dp_read_reg(struct swjdp_common *swjdp, uint32_t *value, uint8_t reg_addr) +static int dap_dp_read_reg(struct swjdp_common *swjdp, + uint32_t *value, uint8_t reg_addr) { - return scan_inout_check_u32(swjdp, DAP_IR_DPACC, reg_addr, DPAP_READ, 0, value); + return scan_inout_check_u32(swjdp, JTAG_DP_DPACC, + reg_addr, DPAP_READ, 0, value); } int dap_ap_select(struct swjdp_common *swjdp,uint8_t apsel) @@ -314,7 +419,7 @@ int dap_ap_select(struct swjdp_common *swjdp,uint8_t apsel) return ERROR_OK; } -int dap_dp_bankselect(struct swjdp_common *swjdp,uint32_t ap_reg) +static int dap_dp_bankselect(struct swjdp_common *swjdp, uint32_t ap_reg) { uint32_t select; select = (ap_reg & 0x000000F0); @@ -328,28 +433,24 @@ int dap_dp_bankselect(struct swjdp_common *swjdp,uint32_t ap_reg) return ERROR_OK; } -int dap_ap_write_reg(struct swjdp_common *swjdp, uint32_t reg_addr, uint8_t* out_value_buf) +static int dap_ap_write_reg(struct swjdp_common *swjdp, + uint32_t reg_addr, uint8_t *out_value_buf) { dap_dp_bankselect(swjdp, reg_addr); - scan_inout_check(swjdp, DAP_IR_APACC, reg_addr, DPAP_WRITE, out_value_buf, NULL); + scan_inout_check(swjdp, JTAG_DP_APACC, reg_addr, + DPAP_WRITE, out_value_buf, NULL); return ERROR_OK; } -int dap_ap_read_reg(struct swjdp_common *swjdp, uint32_t reg_addr, uint8_t *in_value_buf) -{ - dap_dp_bankselect(swjdp, reg_addr); - scan_inout_check(swjdp, DAP_IR_APACC, reg_addr, DPAP_READ, 0, in_value_buf); - - return ERROR_OK; -} int dap_ap_write_reg_u32(struct swjdp_common *swjdp, uint32_t reg_addr, uint32_t value) { uint8_t out_value_buf[4]; buf_set_u32(out_value_buf, 0, 32, value); dap_dp_bankselect(swjdp, reg_addr); - scan_inout_check(swjdp, DAP_IR_APACC, reg_addr, DPAP_WRITE, out_value_buf, NULL); + scan_inout_check(swjdp, JTAG_DP_APACC, reg_addr, + DPAP_WRITE, out_value_buf, NULL); return ERROR_OK; } @@ -357,37 +458,45 @@ int dap_ap_write_reg_u32(struct swjdp_common *swjdp, uint32_t reg_addr, uint32_t int dap_ap_read_reg_u32(struct swjdp_common *swjdp, uint32_t reg_addr, uint32_t *value) { dap_dp_bankselect(swjdp, reg_addr); - scan_inout_check_u32(swjdp, DAP_IR_APACC, reg_addr, DPAP_READ, 0, value); + scan_inout_check_u32(swjdp, JTAG_DP_APACC, reg_addr, + DPAP_READ, 0, value); return ERROR_OK; } -/*************************************************************************** - * * - * AHB-AP access to memory and system registers on AHB bus * - * * -***************************************************************************/ - +/** + * Set up transfer parameters for the currently selected MEM-AP. + * Subsequent transfers using registers like AP_REG_DRW or AP_REG_BD2 + * initiate data reads or writes using memory or peripheral addresses. + * If the CSW is configured for it, the TAR may be automatically + * incremented after each transfer. + * + * @todo Rename to reflect it being specifically a MEM-AP function. + * + * @param swjdp The DAP connected to the MEM-AP. + * @param csw MEM-AP Control/Status Word (CSW) register to assign. If this + * matches the cached value, the register is not changed. + * @param tar MEM-AP Transfer Address Register (TAR) to assign. If this + * matches the cached address, the register is not changed. + */ int dap_setup_accessport(struct swjdp_common *swjdp, uint32_t csw, uint32_t tar) { csw = csw | CSW_DBGSWENABLE | CSW_MASTER_DEBUG | CSW_HPROT; if (csw != swjdp->ap_csw_value) { - /* LOG_DEBUG("swjdp : Set CSW %x",csw); */ + /* LOG_DEBUG("DAP: Set CSW %x",csw); */ dap_ap_write_reg_u32(swjdp, AP_REG_CSW, csw); swjdp->ap_csw_value = csw; } if (tar != swjdp->ap_tar_value) { - /* LOG_DEBUG("swjdp : Set TAR %x",tar); */ + /* LOG_DEBUG("DAP: Set TAR %x",tar); */ dap_ap_write_reg_u32(swjdp, AP_REG_TAR, tar); swjdp->ap_tar_value = tar; } + /* Disable TAR cache when autoincrementing */ if (csw & CSW_ADDRINC_MASK) - { - /* Do not cache TAR value when autoincrementing */ swjdp->ap_tar_value = -1; - } return ERROR_OK; } @@ -413,7 +522,7 @@ int mem_ap_read_atomic_u32(struct swjdp_common *swjdp, uint32_t address, uint32_ { mem_ap_read_u32(swjdp, address, value); - return swjdp_transaction_endcheck(swjdp); + return jtagdp_transaction_endcheck(swjdp); } /***************************************************************************** @@ -437,7 +546,7 @@ int mem_ap_write_atomic_u32(struct swjdp_common *swjdp, uint32_t address, uint32 { mem_ap_write_u32(swjdp, address, value); - return swjdp_transaction_endcheck(swjdp); + return jtagdp_transaction_endcheck(swjdp); } /***************************************************************************** @@ -495,7 +604,7 @@ int mem_ap_write_buf_u32(struct swjdp_common *swjdp, uint8_t *buffer, int count, dap_ap_write_reg(swjdp, AP_REG_DRW, buffer + 4 * writecount); } - if (swjdp_transaction_endcheck(swjdp) == ERROR_OK) + if (jtagdp_transaction_endcheck(swjdp) == ERROR_OK) { wcount = wcount - blocksize; address = address + 4 * blocksize; @@ -516,7 +625,8 @@ int mem_ap_write_buf_u32(struct swjdp_common *swjdp, uint8_t *buffer, int count, return retval; } -int mem_ap_write_buf_packed_u16(struct swjdp_common *swjdp, uint8_t *buffer, int count, uint32_t address) +static int mem_ap_write_buf_packed_u16(struct swjdp_common *swjdp, + uint8_t *buffer, int count, uint32_t address) { int retval = ERROR_OK; int wcount, blocksize, writecount, i; @@ -548,9 +658,12 @@ int mem_ap_write_buf_packed_u16(struct swjdp_common *swjdp, uint8_t *buffer, int if (nbytes < 4) { - if (mem_ap_write_buf_u16(swjdp, buffer, nbytes, address) != ERROR_OK) + if (mem_ap_write_buf_u16(swjdp, buffer, + nbytes, address) != ERROR_OK) { - LOG_WARNING("Block read error address 0x%" PRIx32 ", count 0x%x", address, count); + LOG_WARNING("Block write error address " + "0x%" PRIx32 ", count 0x%x", + address, count); return ERROR_JTAG_DEVICE_ERROR; } @@ -570,9 +683,11 @@ int mem_ap_write_buf_packed_u16(struct swjdp_common *swjdp, uint8_t *buffer, int memcpy(&outvalue, buffer, sizeof(uint32_t)); dap_ap_write_reg_u32(swjdp, AP_REG_DRW, outvalue); - if (swjdp_transaction_endcheck(swjdp) != ERROR_OK) + if (jtagdp_transaction_endcheck(swjdp) != ERROR_OK) { - LOG_WARNING("Block read error address 0x%" PRIx32 ", count 0x%x", address, count); + LOG_WARNING("Block write error address " + "0x%" PRIx32 ", count 0x%x", + address, count); return ERROR_JTAG_DEVICE_ERROR; } } @@ -603,7 +718,7 @@ int mem_ap_write_buf_u16(struct swjdp_common *swjdp, uint8_t *buffer, int count, memcpy(&svalue, buffer, sizeof(uint16_t)); uint32_t outvalue = (uint32_t)svalue << 8 * (address & 0x3); dap_ap_write_reg_u32(swjdp, AP_REG_DRW, outvalue); - retval = swjdp_transaction_endcheck(swjdp); + retval = jtagdp_transaction_endcheck(swjdp); count -= 2; address += 2; buffer += 2; @@ -612,7 +727,8 @@ int mem_ap_write_buf_u16(struct swjdp_common *swjdp, uint8_t *buffer, int count, return retval; } -int mem_ap_write_buf_packed_u8(struct swjdp_common *swjdp, uint8_t *buffer, int count, uint32_t address) +static int mem_ap_write_buf_packed_u8(struct swjdp_common *swjdp, + uint8_t *buffer, int count, uint32_t address) { int retval = ERROR_OK; int wcount, blocksize, writecount, i; @@ -642,7 +758,9 @@ int mem_ap_write_buf_packed_u8(struct swjdp_common *swjdp, uint8_t *buffer, int { if (mem_ap_write_buf_u8(swjdp, buffer, nbytes, address) != ERROR_OK) { - LOG_WARNING("Block read error address 0x%" PRIx32 ", count 0x%x", address, count); + LOG_WARNING("Block write error address " + "0x%" PRIx32 ", count 0x%x", + address, count); return ERROR_JTAG_DEVICE_ERROR; } @@ -662,9 +780,11 @@ int mem_ap_write_buf_packed_u8(struct swjdp_common *swjdp, uint8_t *buffer, int memcpy(&outvalue, buffer, sizeof(uint32_t)); dap_ap_write_reg_u32(swjdp, AP_REG_DRW, outvalue); - if (swjdp_transaction_endcheck(swjdp) != ERROR_OK) + if (jtagdp_transaction_endcheck(swjdp) != ERROR_OK) { - LOG_WARNING("Block read error address 0x%" PRIx32 ", count 0x%x", address, count); + LOG_WARNING("Block write error address " + "0x%" PRIx32 ", count 0x%x", + address, count); return ERROR_JTAG_DEVICE_ERROR; } } @@ -693,7 +813,7 @@ int mem_ap_write_buf_u8(struct swjdp_common *swjdp, uint8_t *buffer, int count, dap_setup_accessport(swjdp, CSW_8BIT | CSW_ADDRINC_SINGLE, address); uint32_t outvalue = (uint32_t)*buffer << 8 * (address & 0x3); dap_ap_write_reg_u32(swjdp, AP_REG_DRW, outvalue); - retval = swjdp_transaction_endcheck(swjdp); + retval = jtagdp_transaction_endcheck(swjdp); count--; address++; buffer++; @@ -734,16 +854,26 @@ int mem_ap_read_buf_u32(struct swjdp_common *swjdp, uint8_t *buffer, int count, dap_setup_accessport(swjdp, CSW_32BIT | CSW_ADDRINC_SINGLE, address); /* Scan out first read */ - adi_jtag_dp_scan(swjdp, DAP_IR_APACC, AP_REG_DRW, DPAP_READ, 0, NULL, NULL); + adi_jtag_dp_scan(swjdp, JTAG_DP_APACC, AP_REG_DRW, + DPAP_READ, 0, NULL, NULL); for (readcount = 0; readcount < blocksize - 1; readcount++) { - /* Scan out read instruction and scan in previous value */ - adi_jtag_dp_scan(swjdp, DAP_IR_APACC, AP_REG_DRW, DPAP_READ, 0, buffer + 4 * readcount, &swjdp->ack); + /* Scan out next read; scan in posted value for the + * previous one. Assumes read is acked "OK/FAULT", + * and CTRL_STAT says that meant "OK". + */ + adi_jtag_dp_scan(swjdp, JTAG_DP_APACC, AP_REG_DRW, + DPAP_READ, 0, buffer + 4 * readcount, + &swjdp->ack); } - /* Scan in last value */ - adi_jtag_dp_scan(swjdp, DAP_IR_DPACC, DP_RDBUFF, DPAP_READ, 0, buffer + 4 * readcount, &swjdp->ack); - if (swjdp_transaction_endcheck(swjdp) == ERROR_OK) + /* Scan in last posted value; RDBUFF has no other effect, + * assuming ack is OK/FAULT and CTRL_STAT says "OK". + */ + adi_jtag_dp_scan(swjdp, JTAG_DP_DPACC, DP_RDBUFF, + DPAP_READ, 0, buffer + 4 * readcount, + &swjdp->ack); + if (jtagdp_transaction_endcheck(swjdp) == ERROR_OK) { wcount = wcount - blocksize; address += 4 * blocksize; @@ -782,7 +912,8 @@ int mem_ap_read_buf_u32(struct swjdp_common *swjdp, uint8_t *buffer, int count, return retval; } -int mem_ap_read_buf_packed_u16(struct swjdp_common *swjdp, uint8_t *buffer, int count, uint32_t address) +static int mem_ap_read_buf_packed_u16(struct swjdp_common *swjdp, + uint8_t *buffer, int count, uint32_t address) { uint32_t invalue; int retval = ERROR_OK; @@ -811,7 +942,7 @@ int mem_ap_read_buf_packed_u16(struct swjdp_common *swjdp, uint8_t *buffer, int do { dap_ap_read_reg_u32(swjdp, AP_REG_DRW, &invalue); - if (swjdp_transaction_endcheck(swjdp) != ERROR_OK) + if (jtagdp_transaction_endcheck(swjdp) != ERROR_OK) { LOG_WARNING("Block read error address 0x%" PRIx32 ", count 0x%x", address, count); return ERROR_JTAG_DEVICE_ERROR; @@ -848,7 +979,7 @@ int mem_ap_read_buf_u16(struct swjdp_common *swjdp, uint8_t *buffer, int count, { dap_setup_accessport(swjdp, CSW_16BIT | CSW_ADDRINC_SINGLE, address); dap_ap_read_reg_u32(swjdp, AP_REG_DRW, &invalue); - retval = swjdp_transaction_endcheck(swjdp); + retval = jtagdp_transaction_endcheck(swjdp); if (address & 0x1) { for (i = 0; i < 2; i++) @@ -877,7 +1008,8 @@ int mem_ap_read_buf_u16(struct swjdp_common *swjdp, uint8_t *buffer, int count, * The solution is to arrange for a large out/in scan in this loop and * and convert data afterwards. */ -int mem_ap_read_buf_packed_u8(struct swjdp_common *swjdp, uint8_t *buffer, int count, uint32_t address) +static int mem_ap_read_buf_packed_u8(struct swjdp_common *swjdp, + uint8_t *buffer, int count, uint32_t address) { uint32_t invalue; int retval = ERROR_OK; @@ -903,7 +1035,7 @@ int mem_ap_read_buf_packed_u8(struct swjdp_common *swjdp, uint8_t *buffer, int c do { dap_ap_read_reg_u32(swjdp, AP_REG_DRW, &invalue); - if (swjdp_transaction_endcheck(swjdp) != ERROR_OK) + if (jtagdp_transaction_endcheck(swjdp) != ERROR_OK) { LOG_WARNING("Block read error address 0x%" PRIx32 ", count 0x%x", address, count); return ERROR_JTAG_DEVICE_ERROR; @@ -940,7 +1072,7 @@ int mem_ap_read_buf_u8(struct swjdp_common *swjdp, uint8_t *buffer, int count, u { dap_setup_accessport(swjdp, CSW_8BIT | CSW_ADDRINC_SINGLE, address); dap_ap_read_reg_u32(swjdp, AP_REG_DRW, &invalue); - retval = swjdp_transaction_endcheck(swjdp); + retval = jtagdp_transaction_endcheck(swjdp); *((uint8_t*)buffer) = (invalue >> 8 * (address & 0x3)); count--; address++; @@ -950,6 +1082,14 @@ int mem_ap_read_buf_u8(struct swjdp_common *swjdp, uint8_t *buffer, int count, u return retval; } +/** + * Initialize a DAP. + * + * @todo Rename this. We also need an initialization scheme which account + * for SWD transports not just JTAG; that will need to address differences + * in layering. (JTAG is useful without any debug target; but not SWD.) + * And this may not even use an AHB-AP ... e.g. DAP-Lite uses an APB-AP. + */ int ahbap_debugport_init(struct swjdp_common *swjdp) { uint32_t idreg, romaddr, dummy; @@ -959,9 +1099,17 @@ int ahbap_debugport_init(struct swjdp_common *swjdp) LOG_DEBUG(" "); + /* Default MEM-AP setup. + * + * REVISIT AP #0 may be an inappropriate default for this. + * Should we probe, or receve a hint from the caller? + * Presumably we can ignore the possibility of multiple APs. + */ swjdp->apsel = 0; swjdp->ap_csw_value = -1; swjdp->ap_tar_value = -1; + + /* DP initialization */ swjdp->trans_mode = TRANS_MODE_ATOMIC; dap_dp_read_reg(swjdp, &dummy, DP_CTRL_STAT); dap_dp_write_reg(swjdp, SSTICKYERR, DP_CTRL_STAT); @@ -977,7 +1125,7 @@ int ahbap_debugport_init(struct swjdp_common *swjdp) /* Check that we have debug power domains activated */ while (!(ctrlstat & CDBGPWRUPACK) && (cnt++ < 10)) { - LOG_DEBUG("swjdp: wait CDBGPWRUPACK"); + LOG_DEBUG("DAP: wait CDBGPWRUPACK"); dap_dp_read_reg(swjdp, &ctrlstat, DP_CTRL_STAT); if ((retval = jtag_execute_queue()) != ERROR_OK) return retval; @@ -986,7 +1134,7 @@ int ahbap_debugport_init(struct swjdp_common *swjdp) while (!(ctrlstat & CSYSPWRUPACK) && (cnt++ < 10)) { - LOG_DEBUG("swjdp: wait CSYSPWRUPACK"); + LOG_DEBUG("DAP: wait CSYSPWRUPACK"); dap_dp_read_reg(swjdp, &ctrlstat, DP_CTRL_STAT); if ((retval = jtag_execute_queue()) != ERROR_OK) return retval; @@ -999,10 +1147,18 @@ int ahbap_debugport_init(struct swjdp_common *swjdp) dap_dp_write_reg(swjdp, swjdp->dp_ctrl_stat, DP_CTRL_STAT); dap_dp_read_reg(swjdp, &dummy, DP_CTRL_STAT); - dap_ap_read_reg_u32(swjdp, 0xFC, &idreg); - dap_ap_read_reg_u32(swjdp, 0xF8, &romaddr); + /* + * REVISIT this isn't actually *initializing* anything in an AP, + * and doesn't care if it's a MEM-AP at all (much less AHB-AP). + * Should it? If the ROM address is valid, is this the right + * place to scan the table and do any topology detection? + */ + dap_ap_read_reg_u32(swjdp, AP_REG_IDR, &idreg); + dap_ap_read_reg_u32(swjdp, AP_REG_BASE, &romaddr); - LOG_DEBUG("AHB-AP ID Register 0x%" PRIx32 ", Debug ROM Address 0x%" PRIx32 "", idreg, romaddr); + LOG_DEBUG("MEM-AP #%d ID Register 0x%" PRIx32 + ", Debug ROM Address 0x%" PRIx32, + swjdp->apsel, idreg, romaddr); return ERROR_OK; } @@ -1025,40 +1181,51 @@ is_dap_cid_ok(uint32_t cid3, uint32_t cid2, uint32_t cid1, uint32_t cid0) && ((cid1 & 0x0f) == 0) && cid0 == 0x0d; } -int dap_info_command(struct command_context *cmd_ctx, struct swjdp_common *swjdp, int apsel) +int dap_info_command(struct command_context *cmd_ctx, + struct swjdp_common *swjdp, int apsel) { - uint32_t dbgbase,apid; + uint32_t dbgbase, apid; int romtable_present = 0; uint8_t mem_ap; uint32_t apselold; + /* AP address is in bits 31:24 of DP_SELECT */ + if (apsel >= 256) + return ERROR_INVALID_ARGUMENTS; + apselold = swjdp->apsel; dap_ap_select(swjdp, apsel); - dap_ap_read_reg_u32(swjdp, 0xF8, &dbgbase); - dap_ap_read_reg_u32(swjdp, 0xFC, &apid); - swjdp_transaction_endcheck(swjdp); + dap_ap_read_reg_u32(swjdp, AP_REG_BASE, &dbgbase); + dap_ap_read_reg_u32(swjdp, AP_REG_IDR, &apid); + jtagdp_transaction_endcheck(swjdp); /* Now we read ROM table ID registers, ref. ARM IHI 0029B sec */ mem_ap = ((apid&0x10000) && ((apid&0x0F) != 0)); - command_print(cmd_ctx, "ap identification register 0x%8.8" PRIx32 "", apid); + command_print(cmd_ctx, "AP ID register 0x%8.8" PRIx32, apid); if (apid) { switch (apid&0x0F) { case 0: - command_print(cmd_ctx, "\tType is jtag-ap"); + command_print(cmd_ctx, "\tType is JTAG-AP"); break; case 1: - command_print(cmd_ctx, "\tType is mem-ap AHB"); + command_print(cmd_ctx, "\tType is MEM-AP AHB"); break; case 2: - command_print(cmd_ctx, "\tType is mem-ap APB"); + command_print(cmd_ctx, "\tType is MEM-AP APB"); break; default: - command_print(cmd_ctx, "\tUnknown AP-type"); - break; + command_print(cmd_ctx, "\tUnknown AP type"); + break; } - command_print(cmd_ctx, "ap debugbase 0x%8.8" PRIx32 "", dbgbase); + + /* NOTE: a MEM-AP may have a single CoreSight component that's + * not a ROM table ... or have no such components at all. + */ + if (mem_ap) + command_print(cmd_ctx, "AP BASE 0x%8.8" PRIx32, + dbgbase); } else { @@ -1083,7 +1250,7 @@ int dap_info_command(struct command_context *cmd_ctx, struct swjdp_common *swjdp mem_ap_read_u32(swjdp, (dbgbase&0xFFFFF000) | 0xFF8, &cid2); mem_ap_read_u32(swjdp, (dbgbase&0xFFFFF000) | 0xFFC, &cid3); mem_ap_read_u32(swjdp, (dbgbase&0xFFFFF000) | 0xFCC, &memtype); - swjdp_transaction_endcheck(swjdp); + jtagdp_transaction_endcheck(swjdp); if (!is_dap_cid_ok(cid3, cid2, cid1, cid0)) command_print(cmd_ctx, "\tCID3 0x%2.2" PRIx32 ", CID2 0x%2.2" PRIx32 @@ -1379,6 +1546,9 @@ DAP_COMMAND_HANDLER(dap_baseaddr_command) break; case 1: COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], apsel); + /* AP address is in bits 31:24 of DP_SELECT */ + if (apsel >= 256) + return ERROR_INVALID_ARGUMENTS; break; default: return ERROR_COMMAND_SYNTAX_ERROR; @@ -1387,8 +1557,13 @@ DAP_COMMAND_HANDLER(dap_baseaddr_command) if (apselsave != apsel) dap_ap_select(swjdp, apsel); - dap_ap_read_reg_u32(swjdp, 0xF8, &baseaddr); - retval = swjdp_transaction_endcheck(swjdp); + /* NOTE: assumes we're talking to a MEM-AP, which + * has a base address. There are other kinds of AP, + * though they're not common for now. This should + * use the ID register to verify it's a MEM-AP. + */ + dap_ap_read_reg_u32(swjdp, AP_REG_BASE, &baseaddr); + retval = jtagdp_transaction_endcheck(swjdp); command_print(CMD_CTX, "0x%8.8" PRIx32, baseaddr); if (apselsave != apsel) @@ -1430,14 +1605,17 @@ DAP_COMMAND_HANDLER(dap_apsel_command) break; case 1: COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], apsel); + /* AP address is in bits 31:24 of DP_SELECT */ + if (apsel >= 256) + return ERROR_INVALID_ARGUMENTS; break; default: return ERROR_COMMAND_SYNTAX_ERROR; } dap_ap_select(swjdp, apsel); - dap_ap_read_reg_u32(swjdp, 0xFC, &apid); - retval = swjdp_transaction_endcheck(swjdp); + dap_ap_read_reg_u32(swjdp, AP_REG_IDR, &apid); + retval = jtagdp_transaction_endcheck(swjdp); command_print(CMD_CTX, "ap %" PRIi32 " selected, identification register 0x%8.8" PRIx32, apsel, apid); @@ -1456,6 +1634,9 @@ DAP_COMMAND_HANDLER(dap_apid_command) break; case 1: COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], apsel); + /* AP address is in bits 31:24 of DP_SELECT */ + if (apsel >= 256) + return ERROR_INVALID_ARGUMENTS; break; default: return ERROR_COMMAND_SYNTAX_ERROR; @@ -1464,8 +1645,8 @@ DAP_COMMAND_HANDLER(dap_apid_command) if (apselsave != apsel) dap_ap_select(swjdp, apsel); - dap_ap_read_reg_u32(swjdp, 0xFC, &apid); - retval = swjdp_transaction_endcheck(swjdp); + dap_ap_read_reg_u32(swjdp, AP_REG_IDR, &apid); + retval = jtagdp_transaction_endcheck(swjdp); command_print(CMD_CTX, "0x%8.8" PRIx32, apid); if (apselsave != apsel) dap_ap_select(swjdp, apselsave);