X-Git-Url: https://review.openocd.org/gitweb?a=blobdiff_plain;f=src%2Ftarget%2Farm_adi_v5.c;h=2695c463b47c275af89f68ab878e2911a6c730a0;hb=8e60d4955f4a89da39bf9b91217c651b44052538;hp=496360f73c844a6985e0032d1aec2ccddd069a60;hpb=7dcde11b459f60d40db9ca53f038cd200c852064;p=openocd.git diff --git a/src/target/arm_adi_v5.c b/src/target/arm_adi_v5.c index 496360f73c..2695c463b4 100644 --- a/src/target/arm_adi_v5.c +++ b/src/target/arm_adi_v5.c @@ -316,12 +316,12 @@ int mem_ap_write_buf_u32(struct adiv5_dap *dap, uint8_t *buffer, int count, uint for (writecount = 0; writecount < blocksize; writecount++) { retval = dap_queue_ap_write(dap, AP_REG_DRW, - *(uint32_t *) (buffer + 4 * writecount)); + *(uint32_t *) ((void *) (buffer + 4 * writecount))); if (retval != ERROR_OK) break; } - if (dap_run(dap) == ERROR_OK) + if ((retval = dap_run(dap)) == ERROR_OK) { wcount = wcount - blocksize; address = address + 4 * blocksize; @@ -335,8 +335,7 @@ int mem_ap_write_buf_u32(struct adiv5_dap *dap, uint8_t *buffer, int count, uint if (errorcount > 1) { LOG_WARNING("Block write error address 0x%" PRIx32 ", wcount 0x%x", address, wcount); - /* REVISIT return the *actual* fault code */ - return ERROR_JTAG_DEVICE_ERROR; + return retval; } } @@ -376,13 +375,14 @@ static int mem_ap_write_buf_packed_u16(struct adiv5_dap *dap, if (nbytes < 4) { - if (mem_ap_write_buf_u16(dap, buffer, - nbytes, address) != ERROR_OK) + retval = mem_ap_write_buf_u16(dap, buffer, + nbytes, address); + if (retval != ERROR_OK) { LOG_WARNING("Block write error address " "0x%" PRIx32 ", count 0x%x", address, count); - return ERROR_JTAG_DEVICE_ERROR; + return retval; } address += nbytes >> 1; @@ -405,13 +405,12 @@ static int mem_ap_write_buf_packed_u16(struct adiv5_dap *dap, if (retval != ERROR_OK) break; - if (dap_run(dap) != ERROR_OK) + if ((retval = dap_run(dap)) != ERROR_OK) { LOG_WARNING("Block write error address " "0x%" PRIx32 ", count 0x%x", address, count); - /* REVISIT return *actual* fault code */ - return ERROR_JTAG_DEVICE_ERROR; + return retval; } } @@ -485,12 +484,13 @@ static int mem_ap_write_buf_packed_u8(struct adiv5_dap *dap, if (nbytes < 4) { - if (mem_ap_write_buf_u8(dap, buffer, nbytes, address) != ERROR_OK) + retval = mem_ap_write_buf_u8(dap, buffer, nbytes, address); + if (retval != ERROR_OK) { LOG_WARNING("Block write error address " "0x%" PRIx32 ", count 0x%x", address, count); - return ERROR_JTAG_DEVICE_ERROR; + return retval; } address += nbytes; @@ -513,13 +513,12 @@ static int mem_ap_write_buf_packed_u8(struct adiv5_dap *dap, if (retval != ERROR_OK) break; - if (dap_run(dap) != ERROR_OK) + if ((retval = dap_run(dap)) != ERROR_OK) { LOG_WARNING("Block write error address " "0x%" PRIx32 ", count 0x%x", address, count); - /* REVISIT return *actual* fault code */ - return ERROR_JTAG_DEVICE_ERROR; + return retval; } } @@ -710,11 +709,12 @@ static int mem_ap_read_buf_packed_u16(struct adiv5_dap *dap, do { retval = dap_queue_ap_read(dap, AP_REG_DRW, &invalue); - if (dap_run(dap) != ERROR_OK) + if (retval != ERROR_OK) + return retval; + if ((retval = dap_run(dap)) != ERROR_OK) { LOG_WARNING("Block read error address 0x%" PRIx32 ", count 0x%x", address, count); - /* REVISIT return the *actual* fault code */ - return ERROR_JTAG_DEVICE_ERROR; + return retval; } nbytes = MIN((readcount << 1), 4); @@ -819,11 +819,12 @@ static int mem_ap_read_buf_packed_u8(struct adiv5_dap *dap, do { retval = dap_queue_ap_read(dap, AP_REG_DRW, &invalue); - if (dap_run(dap) != ERROR_OK) + if (retval != ERROR_OK) + return retval; + if ((retval = dap_run(dap)) != ERROR_OK) { LOG_WARNING("Block read error address 0x%" PRIx32 ", count 0x%x", address, count); - /* REVISIT return the *actual* fault code */ - return ERROR_JTAG_DEVICE_ERROR; + return retval; } nbytes = MIN(readcount, 4); @@ -905,15 +906,18 @@ extern const struct dap_ops jtag_dp_ops; */ int ahbap_debugport_init(struct adiv5_dap *dap) { - uint32_t idreg, romaddr, dummy; uint32_t ctrlstat; int cnt = 0; int retval; LOG_DEBUG(" "); - /* JTAG-DP or SWJ-DP, in JTAG mode */ - dap->ops = &jtag_dp_ops; + /* JTAG-DP or SWJ-DP, in JTAG mode + * ... for SWD mode this is patched as part + * of link switchover + */ + if (!dap->ops) + dap->ops = &jtag_dp_ops; /* Default MEM-AP setup. * @@ -926,7 +930,7 @@ int ahbap_debugport_init(struct adiv5_dap *dap) /* DP initialization */ - retval = dap_queue_dp_read(dap, DP_CTRL_STAT, &dummy); + retval = dap_queue_dp_read(dap, DP_CTRL_STAT, NULL); if (retval != ERROR_OK) return retval; @@ -934,7 +938,7 @@ int ahbap_debugport_init(struct adiv5_dap *dap) if (retval != ERROR_OK) return retval; - retval = dap_queue_dp_read(dap, DP_CTRL_STAT, &dummy); + retval = dap_queue_dp_read(dap, DP_CTRL_STAT, NULL); if (retval != ERROR_OK) return retval; @@ -972,7 +976,7 @@ int ahbap_debugport_init(struct adiv5_dap *dap) alive_sleep(10); } - retval = dap_queue_dp_read(dap, DP_CTRL_STAT, &dummy); + retval = dap_queue_dp_read(dap, DP_CTRL_STAT, NULL); if (retval != ERROR_OK) return retval; /* With debug power on we can activate OVERRUN checking */ @@ -980,26 +984,10 @@ int ahbap_debugport_init(struct adiv5_dap *dap) retval = dap_queue_dp_write(dap, DP_CTRL_STAT, dap->dp_ctrl_stat); if (retval != ERROR_OK) return retval; - retval = dap_queue_dp_read(dap, DP_CTRL_STAT, &dummy); + retval = dap_queue_dp_read(dap, DP_CTRL_STAT, NULL); if (retval != ERROR_OK) return retval; - /* - * REVISIT this isn't actually *initializing* anything in an AP, - * and doesn't care if it's a MEM-AP at all (much less AHB-AP). - * Should it? If the ROM address is valid, is this the right - * place to scan the table and do any topology detection? - */ - retval = dap_queue_ap_read(dap, AP_REG_IDR, &idreg); - retval = dap_queue_ap_read(dap, AP_REG_BASE, &romaddr); - - if ((retval = dap_run(dap)) != ERROR_OK) - return retval; - - LOG_DEBUG("MEM-AP #%" PRId32 " ID Register 0x%" PRIx32 - ", Debug ROM Address 0x%" PRIx32, - dap->apsel, idreg, romaddr); - return ERROR_OK; } @@ -1021,14 +1009,23 @@ is_dap_cid_ok(uint32_t cid3, uint32_t cid2, uint32_t cid1, uint32_t cid0) && ((cid1 & 0x0f) == 0) && cid0 == 0x0d; } -static int dap_info_command(struct command_context *cmd_ctx, - struct adiv5_dap *dap, int apsel) +struct broken_cpu { + uint32_t dbgbase; + uint32_t apid; + uint32_t idcode; + uint32_t correct_dbgbase; + char *model; +} broken_cpus[] = { + { 0x80000000, 0x04770002, 0x1ba00477, 0x60000000, "imx51" }, +}; + +int dap_get_debugbase(struct adiv5_dap *dap, int apsel, + uint32_t *out_dbgbase, uint32_t *out_apid) { - int retval; - uint32_t dbgbase, apid; - int romtable_present = 0; - uint8_t mem_ap; uint32_t apselold; + int retval; + unsigned int i; + uint32_t dbgbase, apid, idcode; /* AP address is in bits 31:24 of DP_SELECT */ if (apsel >= 256) @@ -1036,12 +1033,109 @@ static int dap_info_command(struct command_context *cmd_ctx, apselold = dap->apsel; dap_ap_select(dap, apsel); + retval = dap_queue_ap_read(dap, AP_REG_BASE, &dbgbase); + if (retval != ERROR_OK) + return retval; retval = dap_queue_ap_read(dap, AP_REG_IDR, &apid); + if (retval != ERROR_OK) + return retval; retval = dap_run(dap); if (retval != ERROR_OK) return retval; + /* Excavate the device ID code */ + struct jtag_tap *tap = dap->jtag_info->tap; + while (tap != NULL) { + if (tap->hasidcode) { + idcode = tap->idcode; + break; + } + tap = tap->next_tap; + } + if (tap == NULL || !tap->hasidcode) + return ERROR_OK; + + /* Some CPUs are messed up, so fixup if needed. */ + for (i = 0; i < sizeof(broken_cpus)/sizeof(struct broken_cpu); i++) + if (broken_cpus[i].dbgbase == dbgbase && + broken_cpus[i].apid == apid && + broken_cpus[i].idcode == idcode) { + LOG_WARNING("Found broken CPU (%s), trying to fixup " + "ROM Table location from 0x%08x to 0x%08x", + broken_cpus[i].model, dbgbase, + broken_cpus[i].correct_dbgbase); + dbgbase = broken_cpus[i].correct_dbgbase; + break; + } + + dap_ap_select(dap, apselold); + + /* The asignment happens only here to prevent modification of these + * values before they are certain. */ + *out_dbgbase = dbgbase; + *out_apid = apid; + + return ERROR_OK; +} + +int dap_lookup_cs_component(struct adiv5_dap *dap, int apsel, + uint32_t dbgbase, uint8_t type, uint32_t *addr) +{ + uint32_t apselold; + uint32_t romentry, entry_offset = 0, component_base, devtype; + int retval = ERROR_FAIL; + + if (apsel >= 256) + return ERROR_INVALID_ARGUMENTS; + + apselold = dap->apsel; + dap_ap_select(dap, apsel); + + do + { + retval = mem_ap_read_atomic_u32(dap, (dbgbase&0xFFFFF000) | + entry_offset, &romentry); + if (retval != ERROR_OK) + return retval; + + component_base = (dbgbase & 0xFFFFF000) + + (romentry & 0xFFFFF000); + + if (romentry & 0x1) { + retval = mem_ap_read_atomic_u32(dap, + (component_base & 0xfffff000) | 0xfcc, + &devtype); + if ((devtype & 0xff) == type) { + *addr = component_base; + retval = ERROR_OK; + break; + } + } + entry_offset += 4; + } while (romentry > 0); + + dap_ap_select(dap, apselold); + + return retval; +} + +static int dap_info_command(struct command_context *cmd_ctx, + struct adiv5_dap *dap, int apsel) +{ + int retval; + uint32_t dbgbase, apid; + int romtable_present = 0; + uint8_t mem_ap; + uint32_t apselold; + + retval = dap_get_debugbase(dap, apsel, &dbgbase, &apid); + if (retval != ERROR_OK) + return retval; + + apselold = dap->apsel; + dap_ap_select(dap, apsel); + /* Now we read ROM table ID registers, ref. ARM IHI 0029B sec */ mem_ap = ((apid&0x10000) && ((apid&0x0F) != 0)); command_print(cmd_ctx, "AP ID register 0x%8.8" PRIx32, apid); @@ -1124,7 +1218,9 @@ static int dap_info_command(struct command_context *cmd_ctx, entry_offset = 0; do { - mem_ap_read_atomic_u32(dap, (dbgbase&0xFFFFF000) | entry_offset, &romentry); + retval = mem_ap_read_atomic_u32(dap, (dbgbase&0xFFFFF000) | entry_offset, &romentry); + if (retval != ERROR_OK) + return retval; command_print(cmd_ctx, "\tROMTABLE[0x%x] = 0x%" PRIx32 "",entry_offset,romentry); if (romentry&0x01) { @@ -1140,33 +1236,51 @@ static int dap_info_command(struct command_context *cmd_ctx, /* IDs are in last 4K section */ - mem_ap_read_atomic_u32(dap, + retval = mem_ap_read_atomic_u32(dap, component_base + 0xFE0, &c_pid0); + if (retval != ERROR_OK) + return retval; c_pid0 &= 0xff; - mem_ap_read_atomic_u32(dap, + retval = mem_ap_read_atomic_u32(dap, component_base + 0xFE4, &c_pid1); + if (retval != ERROR_OK) + return retval; c_pid1 &= 0xff; - mem_ap_read_atomic_u32(dap, + retval = mem_ap_read_atomic_u32(dap, component_base + 0xFE8, &c_pid2); + if (retval != ERROR_OK) + return retval; c_pid2 &= 0xff; - mem_ap_read_atomic_u32(dap, + retval = mem_ap_read_atomic_u32(dap, component_base + 0xFEC, &c_pid3); + if (retval != ERROR_OK) + return retval; c_pid3 &= 0xff; - mem_ap_read_atomic_u32(dap, + retval = mem_ap_read_atomic_u32(dap, component_base + 0xFD0, &c_pid4); + if (retval != ERROR_OK) + return retval; c_pid4 &= 0xff; - mem_ap_read_atomic_u32(dap, + retval = mem_ap_read_atomic_u32(dap, component_base + 0xFF0, &c_cid0); + if (retval != ERROR_OK) + return retval; c_cid0 &= 0xff; - mem_ap_read_atomic_u32(dap, + retval = mem_ap_read_atomic_u32(dap, component_base + 0xFF4, &c_cid1); + if (retval != ERROR_OK) + return retval; c_cid1 &= 0xff; - mem_ap_read_atomic_u32(dap, + retval = mem_ap_read_atomic_u32(dap, component_base + 0xFF8, &c_cid2); + if (retval != ERROR_OK) + return retval; c_cid2 &= 0xff; - mem_ap_read_atomic_u32(dap, + retval = mem_ap_read_atomic_u32(dap, component_base + 0xFFC, &c_cid3); + if (retval != ERROR_OK) + return retval; c_cid3 &= 0xff; @@ -1187,9 +1301,11 @@ static int dap_info_command(struct command_context *cmd_ctx, unsigned minor; char *major = "Reserved", *subtype = "Reserved"; - mem_ap_read_atomic_u32(dap, + retval = mem_ap_read_atomic_u32(dap, (component_base & 0xfffff000) | 0xfcc, &devtype); + if (retval != ERROR_OK) + return retval; minor = (devtype >> 4) & 0x0f; switch (devtype & 0x0f) { case 0: @@ -1310,8 +1426,9 @@ static int dap_info_command(struct command_context *cmd_ctx, /* Part number interpretations are from Cortex * core specs, the CoreSight components TRM - * (ARM DDI 0314H), and ETM specs; also from - * chip observation (e.g. TI SDTI). + * (ARM DDI 0314H), CoreSight System Design + * Guide (ARM DGI 0012D) and ETM specs; also + * from chip observation (e.g. TI SDTI). */ part_num = (c_pid0 & 0xff); part_num |= (c_pid1 & 0x0f) << 8; @@ -1381,6 +1498,10 @@ static int dap_info_command(struct command_context *cmd_ctx, type = "Cortex-M3 ETM"; full = "(Embedded Trace)"; break; + case 0x930: + type = "Cortex-R4 ETM"; + full = "(Embedded Trace)"; + break; case 0xc08: type = "Cortex-A8 Debug"; full = "(Debug Unit)"; @@ -1466,6 +1587,8 @@ COMMAND_HANDLER(dap_baseaddr_command) * use the ID register to verify it's a MEM-AP. */ retval = dap_queue_ap_read(dap, AP_REG_BASE, &baseaddr); + if (retval != ERROR_OK) + return retval; retval = dap_run(dap); if (retval != ERROR_OK) return retval; @@ -1529,6 +1652,8 @@ COMMAND_HANDLER(dap_apsel_command) dap_ap_select(dap, apsel); retval = dap_queue_ap_read(dap, AP_REG_IDR, &apid); + if (retval != ERROR_OK) + return retval; retval = dap_run(dap); if (retval != ERROR_OK) return retval; @@ -1567,6 +1692,8 @@ COMMAND_HANDLER(dap_apid_command) dap_ap_select(dap, apsel); retval = dap_queue_ap_read(dap, AP_REG_IDR, &apid); + if (retval != ERROR_OK) + return retval; retval = dap_run(dap); if (retval != ERROR_OK) return retval;